| 書目名稱 | Digital System Verification | | 副標(biāo)題 | A Combined Formal Me | | 編輯 | Lun Li,Mitchell A. Thornton | | 視頻video | http://file.papertrans.cn/280/279731/279731.mp4 | | 叢書名稱 | Synthesis Lectures on Digital Circuits & Systems | | 圖書封面 |  | | 描述 | Integrated circuit capacity follows Moore‘s law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational | | 出版日期 | Book 2010 | | 版次 | 1 | | doi | https://doi.org/10.1007/978-3-031-79815-3 | | isbn_softcover | 978-3-031-79814-6 | | isbn_ebook | 978-3-031-79815-3Series ISSN 1932-3166 Series E-ISSN 1932-3174 | | issn_series | 1932-3166 | | copyright | Springer Nature Switzerland AG 2010 |
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