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Titlebook: Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission; Nereo Markulic,Kuba Raczkowski,Piet Wambacq Book

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發(fā)表于 2025-3-21 19:15:23 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書目名稱Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission
編輯Nereo Markulic,Kuba Raczkowski,Piet Wambacq
視頻videohttp://file.papertrans.cn/280/279724/279724.mp4
概述Guides development of DTC-based Fractional-N Subsampling PLL and Subsampling Polar Transmitters, covering material from fundamental theory, over system level considerations to building block IC implem
叢書名稱Analog Circuits and Signal Processing
圖書封面Titlebook: Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission;  Nereo Markulic,Kuba Raczkowski,Piet Wambacq Book
描述.This book explains concepts behind fractional subsampling-based frequency synthesis that is re-shaping today’s art in the field of low-noise LO generation. It covers advanced material, giving clear guidance for development of background-calibrated environments capable of spur-free synthesis and wideband phase modulation. It further expands the concepts into the field of subsampling polar transmission, where the newly developed architecture enables unprecedented spectral efficiency levels, unquestionably required by the upcoming generation of wireless standards..
出版日期Book 2019
關(guān)鍵詞low-noise LO generation; Digital-to-Time Converter; fractional frequency synthesis; fractional subsampl
版次1
doihttps://doi.org/10.1007/978-3-030-10958-5
isbn_ebook978-3-030-10958-5Series ISSN 1872-082X Series E-ISSN 2197-1854
issn_series 1872-082X
copyrightSpringer Nature Switzerland AG 2019
The information of publication is updating

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發(fā)表于 2025-3-21 22:03:13 | 只看該作者
Christine Strothotte,Thomas Strothotte of operation with practical implementation in mind. The discussion gradually arrives to recently introduced subsampling PLL architectures that tend to overcome typical performance limitations of prior art, offering extreme low-noise synthesis potential.
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A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis,circuit (such as DTC gain variation) are compensated in the digital domain. The prototype achieves a robust fractional lock across the range from 9.2 GHz to 12.7 GHz with less than 280-fs rms integrated jitter (in presence of the worst fractional spur). The total power consumption of the PLL is 13 mW.
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Book 2019eband phase modulation. It further expands the concepts into the field of subsampling polar transmission, where the newly developed architecture enables unprecedented spectral efficiency levels, unquestionably required by the upcoming generation of wireless standards..
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發(fā)表于 2025-3-22 20:00:57 | 只看該作者
Christine Strothotte,Thomas Strothottecircuit (such as DTC gain variation) are compensated in the digital domain. The prototype achieves a robust fractional lock across the range from 9.2 GHz to 12.7 GHz with less than 280-fs rms integrated jitter (in presence of the worst fractional spur). The total power consumption of the PLL is 13 mW.
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1872-082X r transmission, where the newly developed architecture enables unprecedented spectral efficiency levels, unquestionably required by the upcoming generation of wireless standards..978-3-030-10958-5Series ISSN 1872-082X Series E-ISSN 2197-1854
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