Titlebook: Dependable Computing - EDDC-3; Third European Depen Jan Hlavi?ka,Erik Maehle,András Pataricza Conference proceedings 1999 Springer-Verlag B

鋪子

Generator

Software Reliability Engineering Risk Management for the New Milleniumon & knowledge processing systems. In short, SRE seeks to build such systems that do what we want. The question is whether a general risk management (which we want, including the aspects of safety, security, etc.) can be achieved by the approaches used in SRE. If not, why not? If so, how?

ambivalence

Ostrich

gerontocracy

Avoiding Malicious Byzantine Faults by a New Signature Generation Techniqueunder general (and thus hard) fault assumptions. Known signature methods contribute to more efficient solutions by protecting forwarded information from being altered undetectably. This paper presents a new signature generation technique, which prevents the occurrence of malicious Byzantine faults i

漂亮

An Experimental Evaluation of Coordinated Checkpointing in a Parallel Machinefailures. In previous studies it has been proved that this approach achieved better results than independent checkpointing and message logging. However, we need to know more about the real overhead of coordinated checkpointing and get sustained insights about the best way to implement this technique

Stable-Angina

Directed

Assessing Error Detection Coverage by Simulated Fault Injectionult/error handling mechanisms are becoming common features of today servers. This paper presents a new simulated fault injection method, which allows the assessment of the effectiveness of error detection mechanisms without using expensive test circuits. Fault injection was performed in two stages.

Offstage

Considering Workload Input Variations in Error Coverage Estimationn implemented fault injection experiments using the FIMBUL tool on the Thor microprocessor show that the estimated error non-coverage may vary by more than five percentage units for different workload input sequences. A methodology for predicting error coverage for a particular input sequence based

Relinquish

Fault Injection into VHDL Models: Experimental Validation of a Fault-Tolerant Microcomputer Systemd stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed with this purpose. We have carried out a set of injection experiments (with 3000 injections each), injecting transient and permanent faults of types s