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Titlebook: Data Orchestration in Deep Learning Accelerators; Tushar Krishna,Hyoukjun Kwon,Ananda Samajdar Book 2020 Springer Nature Switzerland AG 20

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發(fā)表于 2025-3-21 17:19:43 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書(shū)目名稱Data Orchestration in Deep Learning Accelerators
編輯Tushar Krishna,Hyoukjun Kwon,Ananda Samajdar
視頻videohttp://file.papertrans.cn/263/262986/262986.mp4
叢書(shū)名稱Synthesis Lectures on Computer Architecture
圖書(shū)封面Titlebook: Data Orchestration in Deep Learning Accelerators;  Tushar Krishna,Hyoukjun Kwon,Ananda Samajdar Book 2020 Springer Nature Switzerland AG 20
描述This Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. The End of Moore‘s Law, coupled with the increasing growth in deep learning and other AI applications has led to the emergence of custom Deep Neural Network (DNN) accelerators for energy-efficient inference on edge devices. Modern DNNs have millions of hyper parameters and involve billions of computations; this necessitates extensive data movement from memory to on-chip processing engines. It is well known that the cost of data movement today surpasses the cost of the actual computation; therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM. The book covers DNN dataflows, data reuse, buffer hierarchies, networks-on-chip, and automated design-space exploration. It concludes with data orchestration challenges with compressed and sparse DNNs and future trends. The target audience is students, engineers, and researchers interested in designing high-performance and low-energy accelerators for DNN inference.
出版日期Book 2020
版次1
doihttps://doi.org/10.1007/978-3-031-01767-4
isbn_softcover978-3-031-00639-5
isbn_ebook978-3-031-01767-4Series ISSN 1935-3235 Series E-ISSN 1935-3243
issn_series 1935-3235
copyrightSpringer Nature Switzerland AG 2020
The information of publication is updating

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發(fā)表于 2025-3-21 21:55:53 | 只看該作者
Dataflow and Data Reuse,to billions of computations, we cannot fit all of the computations within an accelerator, which typically has hundreds to thousands of compute units. Therefore, we need to slice the problem into smaller chunks (i.e., computation tiles) and run them in a certain order (i.e., tile scheduling). Within
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發(fā)表于 2025-3-22 01:21:47 | 只看該作者
Buffer Hierarchies,ic accelerators have constraints and goals that differ in key ways. It is important to understand in detail how these cause accelerator architects to make different hardware choices. In this chapter, we present a framework for understanding key options, and explore tradeoffs between design effort an
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發(fā)表于 2025-3-22 07:24:38 | 只看該作者
Networks-on-Chip, contain an array of hundreds of PEs. These accelerators aim to achieve high throughput by exploiting massive parallel computations over the PEs while keeping the cost-of-operation much lower than off-the-shelf components with the same compute budget. However, adding more compute elements in an acce
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發(fā)表于 2025-3-23 00:52:58 | 只看該作者
Buffer Hierarchies,ic accelerators have constraints and goals that differ in key ways. It is important to understand in detail how these cause accelerator architects to make different hardware choices. In this chapter, we present a framework for understanding key options, and explore tradeoffs between design effort and cross-project reuse.
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發(fā)表于 2025-3-23 02:15:42 | 只看該作者
Jason Gu,Rajeeb Dey,Nabanita Adhikaryrovide a brief background on Deep Neural Networks (DNNs), which are the underlying computational mechanisms within Deep Learning applications. Our objective is not to go into the theory behind the structure and accuracy of DNNs (which readers can find in any modern textbook on Machine Learning or De
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發(fā)表于 2025-3-23 06:55:08 | 只看該作者
and the Co-production of Men’s Healthto billions of computations, we cannot fit all of the computations within an accelerator, which typically has hundreds to thousands of compute units. Therefore, we need to slice the problem into smaller chunks (i.e., computation tiles) and run them in a certain order (i.e., tile scheduling). Within
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