Titlebook: Correct Hardware Design and Verification Methods; 10th IFIP WG10.5 Adv Laurence Pierre,Thomas Kropf Conference proceedings 1999 Springer-Ve

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Efficient Verification of Timed Automata Using Dense and Discrete Time Semanticsion. Contrary to some misconceptions, the discrete semantics is not inherently bound to use state-explosive techniques any more than the dense one. In fact, discrete timed automata can be analyzed using any representation scheme (such as DBM) used for dense time, and in addition can benefit from enu

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From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checkingric. We formalize several notions of near symmetry and show how to obtain the benefits of symmetry reduction when applied to asymmetric systems which are nearly symmetric. We show that for some nearly symmetric systems it is possible to perform symmetry reduction and obtain a bisimilar (up to permut

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Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction and industry. In this paper, we present a method for localizing and correcting errors in combinatorial circuits for which equivalence checking has failed. Our approach is general and does not assume any error model. Thus, it allows the detection of arbitrary design errors. Since our method is . str

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Abstract BDDs: A Technique for Using Abstraction in Model Checkingstructure. We show that this technique builds a more refined model than traditional compiler-based methods proposed by Clarke, Grumberg and Long. We also provide experimental results to demonstrate the usefulness of our method. We have verified a pipelined carry-save multiplier and a simple version

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Formal Verification of Designs with Complex Control by Symbolic Simulationication tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall verification time without giving false negatives. The equivalence checker is able to cope with different numb

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Hints to Accelerate Symbolic Traversalrevents its application to large designs. The lack of flexibility of the conventional breadth-first approach to state search is often responsible for the excessive growth of the BDDs. In this paper we show that the use of . to guide the exploration of the state space may result in orders-of-magnitud

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0302-9743 e formal techniques and tools for the design and veri?cation of hardware and systems. Previous conferences have been held in Darmstadt (1984), Edinburgh (1985), Grenoble (1986), Glasgow (1988), Leuven (1989), Torino (1991), Arles (1993), Frankfurt (1995) and Montreal (1997). This workshop and confer