Titlebook: Computer Engineering and Technology; 16th National Confer Weixia Xu,Liquan Xiao,Chengyi Zhang Conference proceedings 2013 Springer-Verlag B

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書目名稱Computer Engineering and Technology影響因子(影響力)




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書目名稱Computer Engineering and Technology網(wǎng)絡(luò)公開度




書目名稱Computer Engineering and Technology網(wǎng)絡(luò)公開度學(xué)科排名




書目名稱Computer Engineering and Technology被引頻次




書目名稱Computer Engineering and Technology被引頻次學(xué)科排名




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書目名稱Computer Engineering and Technology讀者反饋學(xué)科排名

saphenous-vein

Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Methody pseudo-random number generators(PRNG) based on binary linear recurrences. In this paper, a hardware architecture for the generation of parallel long-period random numbers using MT19937 method was proposed. Our design is implemented on a Xilinx XC6VLX240T FPGA device and is capable of producing mul

Modify

MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processoringly important. In this paper, a multi-level hybrid verification platform called MGTE is designed and developed for a 16-core processer PX-16. MGTE supports software simulating and hardware emulating in module level, sub-system level or full-chip level, which is capable of verifying the processor d

脆弱帶來

poliosis

A Study of Cache Design in Stream Processor processor and it aims at exploiting the parallelism and locality of the applications. In this paper, first, we inspect the memory access characteristics of FT64 with cache and without cache. Second, we propose an improved cache design method. Making use of the feature of stream data type used by FT

帽子

Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Procency (like snoopy protocol) or not depending on bus-like interconnects (like directory protocol). Recently, Token Coherence has been proposed to capture the main characteristic of traditional protocols. However, since Token Coherence relies on broadcast-based transient request and inefficient persist

帽子

Desert

ADL and High Performance Processor Designessor design, lots of institutes and companies use ADL as processor quick prototype design language and use it to generate processor simulator, test-benches and compiler utilities. This paper analyzes and compares three processor description languages. We also give the disadvantages of modern ADL wh

弄污

Abutment

A Hardware Implementation of Nussinov RNA Folding Algorithmarallelism of this kind of algorithms is one of the most relevant areas in computational biology. In this paper, we propose a parallel way to implement the Nussinov algorithm on hardware. We implement our work on Xilinx FPGA, the total clock cycles to accomplish the algorithm is about half of using