Titlebook: Computer Architecture; ISCA 2010 Internatio Ana Lucia Varbanescu,Anca Molnos,Rob Nieuwpoort Conference proceedings 2012 Springer-Verlag Gmb

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Performance Impact of Task Mapping on the Cell BE Multicore Processorinterconnect is more complex than a bus. We report on our experiments to map a simple application with communication in a ring to SPEs of a Cell BE processor such that performance is optimized. We find that low-level tricks for static mapping do not necessarily achieve optimal performance. Furthermo

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Implementing a GPU Programming Model on a Non-GPU Accelerator Architectureures without significant performance degradation or code rewrites. While . and its limits have been studied thoroughly on single processor systems, this goal has been less extensively studied and is more difficult to achieve for parallel systems. Emerging single-chip parallel platforms are no except

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On the Use of Small 2D Convolutions on GPUslectromagnetic diffraction modeling in physics. The GPU architecture seems to be a suitable architecture to accelerate these convolutions, but reaching high application performance requires substantial development time and non-portable optimizations. In this work, we present the techniques, performa

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Can Manycores Support the Memory Requirements of Scientific Applications?rt such highly parallel processors..In this paper, we examine the memory bandwidth and footprint required by a number of high-performance scientific applications. We find such applications require a per-core memory bandwidth of ~ 300MB/s, and have a memory footprint of some 300MB per-core..When comp

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Parallelizing an Index Generator for Desktop Searchon three different Intel platforms with 4, 8, and 32 cores. The optimal configurations for these platforms are not intuitive and are markedly different for the three platforms. For finding the optimal configuration, detailed measurements and experimentation were necessary. Several recommendations fo

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Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecksctures is a key challenge. In this work, we present a pintool designed to help evaluate the potential benefit of accelerating a particular function. Our tool gathers cross-procedural data usage patterns, including implicit dependencies not captured by arguments and return values. We then use this da

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Trace Execution Automata in Dynamic Binary Translationized based on the dynamic information derived from the program’s previous runs. The ability to record traces is thus central to any dynamic binary translation system. Recording traces, as well as loading them for use in different runs, requires code replication to represent the trace. This paper pre

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