| 書目名稱 | CMOS PLL Synthesizers: Analysis and Design |
| 編輯 | Keliu Shu,Edgar Sánchez-Sinencio |
| 視頻video | http://file.papertrans.cn/221/220359/220359.mp4 |
| 概述 | Offers a complete coverage of both fundamentals and the state-of-the-art design and analysis techniques of PLL synthesizer |
| 叢書名稱 | The Springer International Series in Engineering and Computer Science |
| 圖書封面 |  |
| 描述 | Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedu |
| 出版日期 | Book 2005 |
| 關鍵詞 | CMOS; PLL; Phase; filter; fractional-N synthesizer; loop capacitance multiplier; phase-switching prescaler |
| 版次 | 1 |
| doi | https://doi.org/10.1007/b102174 |
| isbn_softcover | 978-1-4419-3650-9 |
| isbn_ebook | 978-0-387-23669-8Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Springer-Verlag US 2005 |
|Archiver|手機版|小黑屋|
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