| 期刊全稱 | Behavioral Synthesis and Component Reuse with VHDL | | 影響因子2023 | Ahmed A. Jerraya,Hong Ding,Maher Rahmouni | | 視頻video | http://file.papertrans.cn/183/182897/182897.mp4 | | 圖書(shū)封面 |  | | 影響因子 | Improvement in the quality of integrated circuit designs and adesigner‘s productivity can be achieved by a combination of twofactors: . .Using more structured designmethodologies for extensive reuse of existing components andsubsystems. It seems that 70% of new designs correspond to existingcomponents that cannot be reused because of a lack of methodologiesand tools. ..Providing higher level design tools allowing to startfrom a higher level of abstraction. After the success and thewidespread acceptance of logic and RTL synthesis, the next step isbehavioral synthesis, commonly called architectural or high-levelsynthesis. ....Behavioral Synthesis and Component Reuse with VHDL. providesmethods and techniques for VHDL based behavioral synthesis andcomponent reuse. The goal is to develop VHDL modeling strategies foremerging behavioral synthesis tools. Special attention is given tostructured and modular design methods allowing hierarchical behavioralspecification and design reuse. The goal of this book is not todiscuss behavioral synthesis in general or to discuss a specific toolbut to describe the specific issues related to behavioral synthesis ofVHDL description. .This book targets des | | Pindex | Book 1997 |
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