Titlebook: Asynchronous System-on-Chip Interconnect; John Bainbridge Book 2002 John Bainbridge 2002 Asynchronous.Hardware.Integrated ciruits.Intercon

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Conclusion, growing market in SoC intellectual property. The work described in this book has identified and presented asynchronous solutions to the problems that must be overcome in the design of an on-chip system bus. The work has resulted in the specification of an asynchronous bus architecture for use in such systems.

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https://doi.org/10.1007/978-3-642-91926-8ity whilst minimising design cost and time to market. The key to achieving this goal is a design methodology that allows component reuse. Such methodologies have been an enabling factor in the success of vendors of intellectual property, such as ARM Ltd, who license designs of the same processor cor

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https://doi.org/10.1007/978-3-662-38307-0iques that have been used in larger scale networks are now also being considered for on-chip use. This chapter discusses the basic concepts of a multipoint interconnect, with emphasis on the shared bus which is often favoured for its low hardware cost. Alternative approaches are discussed, but at pr

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us (the first asynchronous SoC bus) used in a commercial demonstrator chip containing a mixture of asynchronous and synchronous macrocells is used as a concrete example throughout the book.978-1-4471-1112-2978-1-4471-0189-5