Titlebook: Architecture of Computing Systems -- ARCS 2014; 27th International C Erik Maehle,Kay R?mer,Eduardo Tovar Conference proceedings 2014 Spring

高原

From Smart Clothing to Smart Table Cloth: Design and Implementation of a Large Scale, Textile Pressu ranging from smart clothing, through smart furniture, to an intelligent table cloth or carpet. The specific functionality and with it most of the complexity lies in the electronics and the processing software. We propose a scalable, modular architecture for such electronics, describe a prototype im

水獺

陶醉

3D DRAM and PCMs in Processor Memory HierarchyRAM as main memory with PCM as backing store and (b) 3D DRAM as the Last Level Cache and PCM as the main memory. In each of these configurations, since the proposed main memories are significantly faster than today’s off-chip 2D DRAMs for main memory and either flash memory based SSDs or magnetic ha

SLING

hemorrhage

Towards Code Safety with High Performancee usually not available in off-the-shelf processors, because of the intrinsic energy costs of hardware duplication or triplication. As an alternative, software schemes based on compiler transformations are used for error detection and recovery. A common software error class caused by hardware transi

不公開

Detecting Compromised Programs for Embedded System Applications are the performance variance and actual program counter values of the embedded processor extracted during program execution. “Cycles per Instruction” is used as pre-processing block before the features are classified using a Self-Organizing Map. Experimental results demonstrate the validity of the

凝乳

https://doi.org/10.1007/978-3-031-27635-4ce-aware Harris corner-detection algorithm for many-core processors. The novel algorithm can adapt itself to the dynamically varying load on a many-core processor to process the frame within a predefined time interval. The results show a 19% improvement in throughput and an 18% improvement in accuracy.

搜集

很是迷惑

https://doi.org/10.1007/3-540-28537-7 us to automatically derive a hardware structure based on access patterns in software, revealed by a static code analysis. This trick reduces the number of hardware details the developer needs to deal with and avoids configuration inconsistencies between the hardware and software levels by design.

Saline

State and economic system regulation for the most important parameters. The generated performance model is able to predict the performance of any other point in the design space with an average prediction error between 1% to 5% for different benchmark applications. This accuracy is achieved by only sampling between 0.0003% to 0.0015% of the full design space.