Titlebook: Architecture of Computing Systems - ARCS 2011; 24th International C Mladen Berekovic,William Fornaciari,Cristina Silva Conference proceedin

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Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3 can be used to optimize code compilation for the microthreaded processor. As the compiler specifies the blocksize parameter for each family of threads individually, it can optimize the register file utilization of the processor.

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Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strateons. To avoid this problem, we propose a novel prefetch scheduling heuristic called . that selectively prioritizes prefetches to open DRAM pages such that performance regressions are minimized. Opportunistic prefetch scheduling reduces performance regressions by 6.7X and 5.2X, while improving perfor

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A Light-Weight Approach for Online State Classification of Self-organizing Parallel Systemsm the information provided by a dedicated, distributed monitoring infrastructure. An important feature of this approach is its capability to self-adapt, i.e., the monitoring infrastructure can adapt the rules to react to given requirements and/or changed system behavior. The proposed method is light

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A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing Systemsand the host system do not share a common memory. Sourcing out the data to the additional hardware thus introduces a communication penalty. Based on a combination of a program’s source code and execution profiling we perform an analysis which evaluates the arithmetic intensity as a cost function to

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Scalability Evaluation of a Polymorphic Register File: A CG Case Studyessor architecture, taking into consideration critical parameters such as cache bandwidth and memory latency. We compare the performance of 256 Polymorphic Register File-augmented workers against a single Cell PowerPC Processor Unit (PPU). In such a scenario, simulation results suggest that for the