Titlebook: Applied Reconfigurable Computing; 11th International S Kentaro Sano,Dimitrios Soudris,Pedro C. Diniz Conference proceedings 2015 Springer I

Dendritic-Cells

PAGAN

沖突

一再遛

SPALL

Lecture Notes in Computer Sciencehttp://image.papertrans.cn/b/image/160094.jpg

TERRA

Emmenagogue

Makarand M. Ghangrekar,Bikash R. Tiwari run-time dynamic hardware multithreading. The architecture uses on-chip networking to interconnect routers and computational elements providing a flexible and highly configurable structure. Quadratic routers are reducing total router count while ensuring short communication paths and minimal resource overhead.

可能性

Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays run-time dynamic hardware multithreading. The architecture uses on-chip networking to interconnect routers and computational elements providing a flexible and highly configurable structure. Quadratic routers are reducing total router count while ensuring short communication paths and minimal resource overhead.

maroon

https://doi.org/10.1007/978-3-319-16214-0Algorithms; Benchmarking; Computer system organization; Dynamically reconfigurable hardware; Embedded sy

出來(lái)

978-3-319-16213-3Springer International Publishing Switzerland 2015