| 書目名稱 | Writing Testbenches: Functional Verification of HDL Models | | 編輯 | Janick Bergeron | | 視頻video | http://file.papertrans.cn/1032/1031358/1031358.mp4 | | 概述 | Includes supplementary material: | | 圖書封面 |  | | 描述 | mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches- all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test- benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today‘s ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification. | | 出版日期 | Book 2003Latest edition | | 關鍵詞 | Factor; Hardware; Hardwarebeschreibungssprache; Interface; Rack; Simulation; SoC; VHDL; Verilog; hardware ver | | 版次 | 2 | | doi | https://doi.org/10.1007/978-1-4615-0302-6 | | isbn_softcover | 978-1-4613-5012-5 | | isbn_ebook | 978-1-4615-0302-6 | | copyright | Kluwer Academic Publishers 2003 |
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