標(biāo)題: Titlebook: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation; 19th International W José Monteiro,René Leuke [打印本頁] 作者: 郊區(qū) 時(shí)間: 2025-3-21 17:29
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書目名稱Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation被引頻次
書目名稱Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation被引頻次學(xué)科排名
書目名稱Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation年度引用
書目名稱Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation年度引用學(xué)科排名
書目名稱Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation讀者反饋
書目名稱Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation讀者反饋學(xué)科排名
作者: Hangar 時(shí)間: 2025-3-21 20:40
Zeqin Wu,Philippe Maurine,Nadine Azemard,Gille Ducharmeomplete and functional lexicon. The text is supported by nearly 170 illustrations and 21 tables to provide detailed and succinct information. I hope and trust that this book will reach the high standard of other gemological dictionaries. If you have criticisms or978-3-662-04288-5作者: 的事物 時(shí)間: 2025-3-22 02:38
Ioannis Kouretas,Vassilis Paliourasomplete and functional lexicon. The text is supported by nearly 170 illustrations and 21 tables to provide detailed and succinct information. I hope and trust that this book will reach the high standard of other gemological dictionaries. If you have criticisms or978-3-662-04288-5作者: brassy 時(shí)間: 2025-3-22 06:05
the information so as to present a complete and functional lexicon. The text is supported by nearly 170 illustrations and 21 tables to provide detailed and succinct information. I hope and trust that this book will reach the high standard of other gemological dictionaries. If you have criticisms or作者: vitrectomy 時(shí)間: 2025-3-22 11:05 作者: 勾引 時(shí)間: 2025-3-22 13:27
Yusuf Leblebici the information so as to present a complete and functional lexicon. The text is supported by nearly 170 illustrations and 21 tables to provide detailed and succinct information. I hope and trust that this book will reach the high standard of other gemological dictionaries. If you have criticisms or作者: 熔巖 時(shí)間: 2025-3-22 21:04
Martin Barnasconi,Markus Damm,Karsten Einwich the information so as to present a complete and functional lexicon. The text is supported by nearly 170 illustrations and 21 tables to provide detailed and succinct information. I hope and trust that this book will reach the high standard of other gemological dictionaries. If you have criticisms or作者: Decibel 時(shí)間: 2025-3-22 21:36
Mohsen Raji,Behnam Ghavami,Hamid R. Zarandi,Hossein Pedram the information so as to present a complete and functional lexicon. The text is supported by nearly 170 illustrations and 21 tables to provide detailed and succinct information. I hope and trust that this book will reach the high standard of other gemological dictionaries. If you have criticisms or作者: organism 時(shí)間: 2025-3-23 05:09 作者: 的事物 時(shí)間: 2025-3-23 06:02 作者: happiness 時(shí)間: 2025-3-23 13:24
SystemC AMS Extensions: New Language – New Methods – New Applicationsof run-time reconfigurable, heterogeneous systems was explained. The various AMS application domains where SystemC-AMS modeling can be applied were presented in the third talk, by Karsten Einwich from Fraunhofer IIS/EAS. The use of SystemC-AMS for the design and verification of Complex Analog/Mixed-作者: Dislocation 時(shí)間: 2025-3-23 15:59
Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlatiotained from a technique that is derived from the principal component analysis (PCA) method. This technique simplifies the computation of mean, variance and covariance values of a set of correlated random variables. In order to consider spatial correlation in the Petri-Net based simulation, we also i作者: micronutrients 時(shí)間: 2025-3-23 20:36
Data-Driven Clock Gating for Digital Filterss technique has been applied on a digital filter used within an ultra low-power industrial design; comparison with other standard and advanced automatic clock-gating methods highlights the effectiveness of the proposed technique.作者: 最有利 時(shí)間: 2025-3-24 00:22 作者: thyroid-hormone 時(shí)間: 2025-3-24 05:43 作者: STAT 時(shí)間: 2025-3-24 07:59
Wei Liu,Andrea Calimera,Alberto Nannarelli,Enrico Macii,Massimo Poncino作者: Indelible 時(shí)間: 2025-3-24 12:12 作者: TAP 時(shí)間: 2025-3-24 16:03 作者: ONYM 時(shí)間: 2025-3-24 20:26 作者: Muffle 時(shí)間: 2025-3-25 02:02 作者: 改正 時(shí)間: 2025-3-25 04:20
Robust Low Power Embedded SRAM Design: From System to Memory Cellscaling for some time was a natural part of technology scaling, which automatically resulted in power reduction. For sub-100nm technologies it has been difficult to reduce active power consumption for SRAMs, because the amount of memory in digital ICs is still increasing and the memory bit cell does作者: GROG 時(shí)間: 2025-3-25 08:29
Variability in Advanced Nanometer Technologies: Challenges and SolutionsDue to the difficulty in process control in advanced nanometer technologies, manufacturing-induced variations are growing both in number and as a percentage of device feature sizes, and a deep understanding of the different sources of variation, along with their characterization and modeling, has be作者: Cabg318 時(shí)間: 2025-3-25 14:41
Subthreshold Circuit Design for Ultra-Low-Power Applicationsting in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down li作者: 蛙鳴聲 時(shí)間: 2025-3-25 17:24 作者: convulsion 時(shí)間: 2025-3-25 23:19 作者: 鎮(zhèn)痛劑 時(shí)間: 2025-3-26 03:35 作者: 誰在削木頭 時(shí)間: 2025-3-26 04:31 作者: flaggy 時(shí)間: 2025-3-26 10:03
Exponent Monte Carlo for Quick Statistical Circuit Simulationr verifying high circuit yield in the presence of random process variations. Results on industry-grade standard cell netlists and compact models in 45nm show that EMC predicts reasonable results at least 1,000 times faster than MC.作者: EXALT 時(shí)間: 2025-3-26 15:40
Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesison in current clock tree synthesis algorithms. It is based on the timing characterization of a reference inverter, which can be performed for different process corners to account for process variability. Simulation results show that the model is accurate to within 10% for the most common inverter an作者: BIBLE 時(shí)間: 2025-3-26 19:12 作者: 滑稽 時(shí)間: 2025-3-26 21:18 作者: 誘導(dǎo) 時(shí)間: 2025-3-27 03:49
Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. Power consumption is a critical issue in interconnection network in NoC design, driven by power-related design constraints, such as thermal and power delivery design. In this work, we introdu作者: 調(diào)整校對(duì) 時(shí)間: 2025-3-27 06:05
Data-Driven Clock Gating for Digital Filterslassical low-power optimizations that exploit idleness, such as clock gating..In this work, we propose a data-driven implementation of clock gating for digital filters, which relies on the observation that often times the dynamic range of the inputs uses only a small portion of the bidwith, resultin作者: NOMAD 時(shí)間: 2025-3-27 11:39 作者: exclusice 時(shí)間: 2025-3-27 17:03
Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systemsltiprocessor systems. With the increase in number of processors, there is an increased demand to efficiently control the energy and power budget of such embedded systems. Dynamic Power Management (DPM) strategies attempt to control this budget by actively changing the power consumption profile of th作者: gastritis 時(shí)間: 2025-3-27 19:43
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold wir SOC application using 90nm multi-threshold CMOS technology. Via the HVT/BP-DTMOS-DT-type logic cell technique generated by the special gate-level dual-threshold static power optimization methodology (GDSPOM) procedure, a 0.5V 16-bit multiplier circuit has been designed and optimized, consuming 22%作者: dictator 時(shí)間: 2025-3-28 00:29 作者: Vertebra 時(shí)間: 2025-3-28 03:23
Modeling and Reducing EMI in GALS and Synchronous Systemsseveral different abstract models of GALS circuits have been designed in order to extract a realistic pausable clock behavior. Based on the clock behavior, we have been able to analyze using our tool the current profile of each modeled system, both in frequency and in time domain. The results have b作者: 返老還童 時(shí)間: 2025-3-28 08:05 作者: inquisitive 時(shí)間: 2025-3-28 12:25
Toby Doorn,Roelof Saltersrmation generated in the science of Gemology has increased tremendously. Therefore this book "Dictionary of Gems and Gemology" was written with the aim of providing a "relatively" complete dictionary to assist all students, hobbyists, scientists and interested parties in the fields of Gems and Gemol作者: 粗野 時(shí)間: 2025-3-28 15:15
Davide Pandiniand Gemology" was written with the aim of providing a "relatively" complete dictionary to assist all students, hobbyists, scientists and interested parties in the fields of Gems and Gemology. The forerunner to this book was called "Dictionary of Gems and Gemology" (English-Persian, Persian-English, 作者: PET-scan 時(shí)間: 2025-3-28 18:44
Yusuf Leblebiciand Gemology" was written with the aim of providing a "relatively" complete dictionary to assist all students, hobbyists, scientists and interested parties in the fields of Gems and Gemology. The forerunner to this book was called "Dictionary of Gems and Gemology" (English-Persian, Persian-English, 作者: 絕緣 時(shí)間: 2025-3-29 01:13 作者: compose 時(shí)間: 2025-3-29 06:31 作者: CRANK 時(shí)間: 2025-3-29 09:52 作者: 沙漠 時(shí)間: 2025-3-29 12:15
Ioannis Kouretas,Vassilis Paliourasrmation generated in the science of Gemology has increased tremendously. Therefore this book "Dictionary of Gems and Gemology" was written with the aim of providing a "relatively" complete dictionary to assist all students, hobbyists, scientists and interested parties in the fields of Gems and Gemol作者: expeditious 時(shí)間: 2025-3-29 19:01 作者: cunning 時(shí)間: 2025-3-29 22:56 作者: handle 時(shí)間: 2025-3-30 03:12
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold wial-threshold static power optimization methodology (GDSPOM) procedure, a 0.5V 16-bit multiplier circuit has been designed and optimized, consuming 22% less static leakage power at the operating frequency of 400MHz as compared to the HVT/LVT-type counterpart optimized by the GDSPOM reported before.作者: cogent 時(shí)間: 2025-3-30 06:02 作者: infinite 時(shí)間: 2025-3-30 10:15
Modeling and Reducing EMI in GALS and Synchronous Systemseen compared with the synchronous counterparts including low-EMI solutions. As a result, a reduction up to 25 dB can be achieved when applying a low-EMI GALS methodology in comparison to the synchronous designs.作者: DALLY 時(shí)間: 2025-3-30 12:51
Conference proceedings 2010 sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.作者: 充足 時(shí)間: 2025-3-30 19:45
Power Management and Its Impact on Power Supply Noiseesign under different workloads and operating frequencies. A series of case studies will be presented to illustrate the effect of power management operations on transient noise and the design of a power management control unit to contain voltage droop.作者: 和諧 時(shí)間: 2025-3-30 21:04 作者: CREST 時(shí)間: 2025-3-31 03:33
0302-9743 hniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.978-3-642-11801-2978-3-642-11802-9Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: acrophobia 時(shí)間: 2025-3-31 05:25
Subthreshold Circuit Design for Ultra-Low-Power Applicationsa supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ (Femto-Joule = 10E-15 J) per gate. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology were presented.作者: 共同確定為確 時(shí)間: 2025-3-31 11:07 作者: 笨拙處理 時(shí)間: 2025-3-31 14:55 作者: 高調(diào) 時(shí)間: 2025-3-31 19:45
Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systemsal DPM approaches often yield suboptimal, if not incorrect, performance in the presence of real time constraints. Our strategy gives better energy consumption performance under the same constraints by 10.40%. Also, it reduces the number of overall state transitions by 74.85% and 59.76% for EDF and LLF scheduling policies respectively.作者: 培養(yǎng) 時(shí)間: 2025-3-31 23:53
0302-9743 ization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized 作者: Retrieval 時(shí)間: 2025-4-1 02:49 作者: Fermentation 時(shí)間: 2025-4-1 09:11
Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation978-3-642-11802-9Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: 舊石器時(shí)代 時(shí)間: 2025-4-1 13:57
Lecture Notes in Computer Sciencehttp://image.papertrans.cn/i/image/468454.jpg作者: 蒸發(fā) 時(shí)間: 2025-4-1 16:38
A Hardware Implementation of the User-Centric Display Energy ManagementThis paper introduces a hardware system for user-centric display energy management. From the camera readings, the system detects the user presence and gaze and produces signals that control the display backlight. Experiments show that the system operates in real-time, has 88% detection accuracy and consumes less than 1W of power.作者: cravat 時(shí)間: 2025-4-1 20:16
