標(biāo)題: Titlebook: Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors; José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Bo [打印本頁(yè)] 作者: 連結(jié) 時(shí)間: 2025-3-21 19:18
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作者: 乞討 時(shí)間: 2025-3-22 00:19
Conclusions and Future Work,ent levels to achieve high fault detection rates. In spite of that, the main disadvantages were the intrusiveness of most of hardware-based and hybrid techniques and the performance degradations and memory overhead of software-based techniques.作者: 頭腦冷靜 時(shí)間: 2025-3-22 00:23 作者: guardianship 時(shí)間: 2025-3-22 06:36
discuss the best trade-off between software-based and hardware-based techniques and introduce novel hybrid techniques. Proposed techniques increase existing fault detection rates up to 100%, while maintaining low performance overheads in area and application execution time..978-3-319-35997-7978-3-319-06340-9作者: 放氣 時(shí)間: 2025-3-22 09:27
Introduction,s and a personal computer can be found in any cell phone. One the other hand, a few things remained the same, such as the old topic on how to give a system the ability to cope with a fault and continue its correct operation, or in other words, fault tolerance.作者: 火光在搖曳 時(shí)間: 2025-3-22 15:41 作者: 誘拐 時(shí)間: 2025-3-22 18:31 作者: 廢墟 時(shí)間: 2025-3-22 23:40
Book 2014e degradation and increase error detection when associated with applications implemented in embedded processors. ?Coverage begins with an extensive discussion of the current state-of-the-art in fault tolerance techniques.? The authors then discuss the best trade-off between software-based and hardwa作者: innovation 時(shí)間: 2025-3-23 02:27 作者: venous-leak 時(shí)間: 2025-3-23 07:21
Fault Tolerance Techniques for Processors,ware-based techniques and (3) hybrid techniques. Fault tolerance techniques can be applied at different levels of implementation, starting from the software level down to the architecture description level, the logical and transistor level, until the layout level. In this book, we will focus on hybrid techniques applied at software level.作者: PUT 時(shí)間: 2025-3-23 11:34
Proposed Techniques to Detect Transient Faults in Processors,ues cannot protect processors without at least doubling its area. On the other hand, combined into hybrid techniques, they can not only present increase their detection rates, but also be optimized into achieving a better tradeoff between area overhead and performance degradation, and fault detection.作者: invade 時(shí)間: 2025-3-23 15:59 作者: 性別 時(shí)間: 2025-3-23 21:54
978-3-319-35997-7Springer International Publishing Switzerland 2014作者: 改革運(yùn)動(dòng) 時(shí)間: 2025-3-24 02:14 作者: 瑣碎 時(shí)間: 2025-3-24 05:31
http://image.papertrans.cn/h/image/430083.jpg作者: Daily-Value 時(shí)間: 2025-3-24 07:28
Background,This chapter introduces the main technical terms used in this text, describes the microprocessor architecture used as a case study, and discusses background information required for better enlightenment of the topics in this book.作者: BILE 時(shí)間: 2025-3-24 11:38
José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Becker作者: Inexorable 時(shí)間: 2025-3-24 18:22
José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Becker作者: parsimony 時(shí)間: 2025-3-24 22:17 作者: 遺留之物 時(shí)間: 2025-3-25 01:25 作者: 寬敞 時(shí)間: 2025-3-25 05:53 作者: Substance 時(shí)間: 2025-3-25 10:14
José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Becker作者: CLAP 時(shí)間: 2025-3-25 12:14
José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Becker作者: 使苦惱 時(shí)間: 2025-3-25 19:53
José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Becker作者: GILD 時(shí)間: 2025-3-25 23:18
Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors作者: Obverse 時(shí)間: 2025-3-26 02:38 作者: 空氣傳播 時(shí)間: 2025-3-26 07:10
Introduction,tant topic of interest. In the early ages of computers, their usage was very specific calculations, and aimed at activities such as military applications, precise calculations, and space missions. An error in these applications working in such harsh environments, and sometimes even in remote places 作者: textile 時(shí)間: 2025-3-26 08:39
Fault Tolerance Techniques for Processors,ware-based techniques and (3) hybrid techniques. Fault tolerance techniques can be applied at different levels of implementation, starting from the software level down to the architecture description level, the logical and transistor level, until the layout level. In this book, we will focus on hybr作者: 粗野 時(shí)間: 2025-3-26 13:40 作者: BRIDE 時(shí)間: 2025-3-26 17:52
Simulation Fault Injection Experimental Results,by adding upsets when simulating a given system in commercial simulators, such as ModelSim from Mentor or iSim from Xilinx, or open source simulators, such as Spice. They are able to provide the best control over the experiment. This characteristic is because the simulation can be stopped at any sim作者: 中子 時(shí)間: 2025-3-26 22:13 作者: Feedback 時(shí)間: 2025-3-27 02:31 作者: Rheumatologist 時(shí)間: 2025-3-27 07:14
Conclusions and Future Work,iment. In Chap. 3 we presented the related works through fault tolerant techniques. These works showed different approaches to deal with transient faults at hardware, software and hybrid levels. They presented interesting concepts and proved the advantage of using fault tolerant techniques at differ作者: savage 時(shí)間: 2025-3-27 10:09 作者: Bouquet 時(shí)間: 2025-3-27 14:19 作者: 獨(dú)特性 時(shí)間: 2025-3-27 18:47 作者: 假 時(shí)間: 2025-3-28 00:11 作者: 量被毀壞 時(shí)間: 2025-3-28 06:11 作者: 不適當(dāng) 時(shí)間: 2025-3-28 09:48
,Pr?natale Diagnostik heute,nd auch heute in der Regel zun?chst übersteigert, bedingt durch mangelhafte Sachkenntnis, Betroffenheit und überraschung. Es folgt dann zumeist eine sehr lange und schmerzvolle Zeit, bis sich die Spreu vom Weizen gesondert und sich ein neues Weltbild geformt hat.作者: 不要嚴(yán)酷 時(shí)間: 2025-3-28 12:11 作者: ferment 時(shí)間: 2025-3-28 15:17 作者: 癡呆 時(shí)間: 2025-3-28 20:36
