標(biāo)題: Titlebook: Design and Testing of Reversible Logic; Ashutosh Kumar Singh,Masahiro Fujita,Anand Mohan Book 2020 Springer Nature Singapore Pte Ltd. 2020 [打印本頁(yè)] 作者: Agitated 時(shí)間: 2025-3-21 17:45
書目名稱Design and Testing of Reversible Logic影響因子(影響力)
書目名稱Design and Testing of Reversible Logic影響因子(影響力)學(xué)科排名
書目名稱Design and Testing of Reversible Logic網(wǎng)絡(luò)公開度
書目名稱Design and Testing of Reversible Logic網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱Design and Testing of Reversible Logic被引頻次
書目名稱Design and Testing of Reversible Logic被引頻次學(xué)科排名
書目名稱Design and Testing of Reversible Logic年度引用
書目名稱Design and Testing of Reversible Logic年度引用學(xué)科排名
書目名稱Design and Testing of Reversible Logic讀者反饋
書目名稱Design and Testing of Reversible Logic讀者反饋學(xué)科排名
作者: Harpoon 時(shí)間: 2025-3-21 22:01 作者: 主動(dòng) 時(shí)間: 2025-3-22 02:38 作者: 抗生素 時(shí)間: 2025-3-22 07:45
Hiroshige Inazumi,Shigeichi Hirasawalty area. A limitation for the second testing scheme is that it can only be employed over a specific type of reversible circuit known as Exclusive-Or Sum-Of-Product (ESOP) design. Both the testing techniques have been executed over different benchmark suites and a comparative study with state-of-the作者: FER 時(shí)間: 2025-3-22 11:28
Mathematical Foundations in Visualizatione analyzed for single stuck-at faults in molecular QCA circuit. Our proposed latches are able to examine single stuck-at fault, missing/additional QCA cell defect online, including permanent or transient fault in molecular QCA and efficient respect to circuit area. The designs of QCA layouts for var作者: hemorrhage 時(shí)間: 2025-3-22 13:19
Foundations of Data Visualization. The design algorithm has been partitioned into three phases of qubit selection, qubit placement and SWAP gate implementation. To verify the exactness of the stated design approach, its functionality has been evaluated over a wide set of benchmark function and subsequently witnessed an improvement 作者: hemorrhage 時(shí)間: 2025-3-22 20:54
G. Elisabeta Marai,Torsten M?llerThe multilayer crossing reduces the number of cells required for realization and also it passes the signal without any degradation. The simulation results confirm that the proposed router consumes minimum resources for its realization (up to 50% improvement) than the existing. The nano router is sui作者: 樸素 時(shí)間: 2025-3-22 22:26 作者: 宣傳 時(shí)間: 2025-3-23 01:47 作者: 災(zāi)難 時(shí)間: 2025-3-23 09:18
Fault Models and Test Approaches in Reversible Logic Circuitsted under two extensive classifications to meet the challenge. The methodologies are alleged to coat almost all the faults and their sub kind by exploiting the properties of reversible gates and circuits. The objective is to minimize testing overhead, which can be achieved by reducing the cost metri作者: 停止償付 時(shí)間: 2025-3-23 10:12
Detection and Identification of Gate Faults in Reversible Circuitlty area. A limitation for the second testing scheme is that it can only be employed over a specific type of reversible circuit known as Exclusive-Or Sum-Of-Product (ESOP) design. Both the testing techniques have been executed over different benchmark suites and a comparative study with state-of-the作者: JOG 時(shí)間: 2025-3-23 14:47
Online Testable Efficient Latches for Molecular QCA Based on Reversible Logice analyzed for single stuck-at faults in molecular QCA circuit. Our proposed latches are able to examine single stuck-at fault, missing/additional QCA cell defect online, including permanent or transient fault in molecular QCA and efficient respect to circuit area. The designs of QCA layouts for var作者: Guaff豪情痛飲 時(shí)間: 2025-3-23 20:59
An Efficient Nearest Neighbor Design for 2D Quantum Circuits. The design algorithm has been partitioned into three phases of qubit selection, qubit placement and SWAP gate implementation. To verify the exactness of the stated design approach, its functionality has been evaluated over a wide set of benchmark function and subsequently witnessed an improvement 作者: PANIC 時(shí)間: 2025-3-23 23:18 作者: GRAIN 時(shí)間: 2025-3-24 02:53 作者: 弄污 時(shí)間: 2025-3-24 10:04 作者: 音的強(qiáng)弱 時(shí)間: 2025-3-24 14:11
On the Complexity of File Allocation Problemsimilarly formulated as QBF. We show various experiments to demonstrate how the method can correct the circuits with an implementation on the logic synthesis and verification tool, ABC from University of California, Berkeley. The discussed methods can be extended to topologically constraints reversible circuit synthesis.作者: 不可磨滅 時(shí)間: 2025-3-24 17:50 作者: 無(wú)辜 時(shí)間: 2025-3-24 18:59
https://doi.org/10.1007/978-3-030-25335-6 task for existing synthesis algorithms. The proposed algorithm has been applied to synthesize all 3-variable reversible functions and has shown to obtain a good result. From the experimental results, it has been shown that with the m-NCT gate library added, the results are improved significantly.作者: 易發(fā)怒 時(shí)間: 2025-3-25 02:58
Foundations of Dependable Computingrter. Feynman gate is used as a fundamental building block to perform the proposed design of code converter. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. QCAPro, a very widespread power estimator simulation engine, is applied to estimate the power depletion of the proposed circuit.作者: nautical 時(shí)間: 2025-3-25 07:02
Search-Based Reversible Logic Synthesis Using Mixed-Polarity Gates task for existing synthesis algorithms. The proposed algorithm has been applied to synthesize all 3-variable reversible functions and has shown to obtain a good result. From the experimental results, it has been shown that with the m-NCT gate library added, the results are improved significantly.作者: 比喻好 時(shí)間: 2025-3-25 10:00
Design of Reversible Binary-to-Gray Code Converter in Quantum-Dot Cellular Automatarter. Feynman gate is used as a fundamental building block to perform the proposed design of code converter. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. QCAPro, a very widespread power estimator simulation engine, is applied to estimate the power depletion of the proposed circuit.作者: 確定 時(shí)間: 2025-3-25 15:41 作者: 敏捷 時(shí)間: 2025-3-25 16:11
Automatic Error Correction of Reversible Circuitssimilarly formulated as QBF. We show various experiments to demonstrate how the method can correct the circuits with an implementation on the logic synthesis and verification tool, ABC from University of California, Berkeley. The discussed methods can be extended to topologically constraints reversible circuit synthesis.作者: IRS 時(shí)間: 2025-3-25 23:36
Book 2020ges and the reversible logic circuits to meet these challenges stimulated during each stage of work cycle. The novel computing paradigms are being explored to serve as a basis for fast and low power computation.作者: parsimony 時(shí)間: 2025-3-26 02:10
https://doi.org/10.1007/978-3-642-68952-9arbage output (GO), power and quantum cost (QC) as well as the delay than that of existing designs. This work can offer a vital step in the design of reversible designs for in the field of image processing. It could also be present as an essential step in this area since the image processing systems are known to be the biggest energy consumers.作者: myelography 時(shí)間: 2025-3-26 05:03 作者: Hamper 時(shí)間: 2025-3-26 09:16
1876-1100 e of work cycle. The novel computing paradigms are being explored to serve as a basis for fast and low power computation.978-981-13-8823-1978-981-13-8821-7Series ISSN 1876-1100 Series E-ISSN 1876-1119 作者: FELON 時(shí)間: 2025-3-26 13:58 作者: 不真 時(shí)間: 2025-3-26 19:46 作者: PLIC 時(shí)間: 2025-3-26 22:47 作者: 諷刺 時(shí)間: 2025-3-27 02:18
https://doi.org/10.1007/978-981-13-8821-7Reversible Logic Circuits; Design & Automation; Design for Testability; Fault Tolerance Computing; Emerg作者: GUEER 時(shí)間: 2025-3-27 09:10 作者: Obstacle 時(shí)間: 2025-3-27 10:12 作者: OMIT 時(shí)間: 2025-3-27 13:42 作者: Scleroderma 時(shí)間: 2025-3-27 21:35 作者: 虛情假意 時(shí)間: 2025-3-28 01:11 作者: 宏偉 時(shí)間: 2025-3-28 05:44 作者: Plaque 時(shí)間: 2025-3-28 06:24
https://doi.org/10.1007/978-3-642-68952-9is wasted in this approach, i.e., it performs a bijective function. This chapter introduces a hardware design of reversible BinDCT. It is a new proposal in reversible approach. In this study, we dealt with a variety of sub-modules, which have a better performance in terms of constant inputs (CIs), g作者: 歹徒 時(shí)間: 2025-3-28 11:06
Foundations of Constructive Mathematicsreversible gates are considered to implement 4-bit counter. Performance of the proposed 33 gate is verified using thirteen standard three variables Boolean functions, which demonstrate from 17.8 to 45.2% superiority in term of gate counts obtained with other reversible gates. New structures for T fl作者: aspect 時(shí)間: 2025-3-28 16:46
Foundations of Constructive Mathematicsof attaining low power consuming design techniques breeds the concept of reversible circuit design. One such computing paradigm that enforces reversibility in design architecture is quantum computation. Since a couple of years, several researches are going to make the reversible designs improved fur作者: 連鎖,連串 時(shí)間: 2025-3-28 20:10
Dry Eye Disease: A Modern History and the difference of logic synthesis methods for general CMOS circuits and reversible circuits are clarified. Then logic synthesis methods for reversible circuits based on exhaustive search, repetition of local circuit transformations, Binary Decision Diagram (BDD) based approaches, SAT-based meth作者: Certainty 時(shí)間: 2025-3-28 23:26
https://doi.org/10.1007/978-3-030-25335-6 of reversible circuits using its Positive-Polarity Reed–Muller (PPRM) expansions is presented in this chapter. The proposed algorithm used Hamming Distance (HD) approach to select the transformation path. A variety of reversible gates are selected through finding the possible matching reversible ga作者: adumbrate 時(shí)間: 2025-3-29 06:07 作者: sparse 時(shí)間: 2025-3-29 10:56 作者: 招惹 時(shí)間: 2025-3-29 13:00
On the Complexity of File Allocation Problemn be categorized into two behavioral schemes: (i) Online testing, where the detection of faults within the circuit is carried out during its operation, (ii) Offline testing, where test vectors are applied after extracting the circuit out from its normal operation and the correct output values are kn作者: Blanch 時(shí)間: 2025-3-29 17:53 作者: 東西 時(shí)間: 2025-3-29 20:03
Mathematical Foundations in Visualizationed models for quantum computation are quantum dot cellular automata (QCA). The molecular QCA has the tendency to high error rates. In case of molecular quantum dot cellular automata, the main objective of circuit design is the reduction of circuit area with wanted functional behavior. In this articl作者: committed 時(shí)間: 2025-3-30 01:40
Foundations of Data Visualizationt and powerful computational technology called “quantum computing”. But physical implementation of these circuits considers the nearest neighbor qubit interaction as the desirable one otherwise a computational error can result. Realization of such an architecture in which qubit interacts only with i作者: 可能性 時(shí)間: 2025-3-30 07:31
G. Elisabeta Marai,Torsten M?llerA), which are called as quantum circuits. The router is a predominant device in the modern communication era. The router is expected to perform faster with minimum area requirement and power consumption. In this paper, a nano router is designed in reversible logic and it is realized in quantum cellu作者: 人充滿活力 時(shí)間: 2025-3-30 10:49
Foundations of Dependable Computing an incipient nanotechnology, which leads to build circuits at nanoscale. It offers various features such as minimal power dissipation, very high-operating frequency, and nanoscale feature size. Besides, reversible computation can lead to the development of low-power systems without loss of informat作者: 騎師 時(shí)間: 2025-3-30 13:12 作者: Bother 時(shí)間: 2025-3-30 19:33 作者: hazard 時(shí)間: 2025-3-30 23:20
