標(biāo)題: Titlebook: Delay Fault Testing for VLSI Circuits; Angela Krsti?,Kwang-Ting Cheng Book 1998 Springer Science+Business Media New York 1998 VLSI.compute [打印本頁(yè)] 作者: 法庭 時(shí)間: 2025-3-21 17:17
書(shū)目名稱(chēng)Delay Fault Testing for VLSI Circuits影響因子(影響力)
書(shū)目名稱(chēng)Delay Fault Testing for VLSI Circuits影響因子(影響力)學(xué)科排名
書(shū)目名稱(chēng)Delay Fault Testing for VLSI Circuits網(wǎng)絡(luò)公開(kāi)度
書(shū)目名稱(chēng)Delay Fault Testing for VLSI Circuits網(wǎng)絡(luò)公開(kāi)度學(xué)科排名
書(shū)目名稱(chēng)Delay Fault Testing for VLSI Circuits被引頻次
書(shū)目名稱(chēng)Delay Fault Testing for VLSI Circuits被引頻次學(xué)科排名
書(shū)目名稱(chēng)Delay Fault Testing for VLSI Circuits年度引用
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書(shū)目名稱(chēng)Delay Fault Testing for VLSI Circuits讀者反饋
書(shū)目名稱(chēng)Delay Fault Testing for VLSI Circuits讀者反饋學(xué)科排名
作者: 爭(zhēng)論 時(shí)間: 2025-3-21 21:05
Path Delay Fault Classification, a test exists. Given various path sensitization criteria, paths are generally classified into several classes: single-path sensitizable, robust, non-robust, functional sensitizable and functional unsensitizable.作者: 手勢(shì) 時(shí)間: 2025-3-22 03:27 作者: bisphosphonate 時(shí)間: 2025-3-22 05:00 作者: Chagrin 時(shí)間: 2025-3-22 12:11
Conclusions and Future Work,“noise faults” such as: distributed delay defects, power bus noise, ground bounce, substrate noise and crosstalk. Analysis shows that excessive noise most of the time leads to delay faults [19]. For example, studies have shown that the increased coupling effects produce interference between signals 作者: 形容詞詞尾 時(shí)間: 2025-3-22 16:06
Die Bedeutung der gest?rten Nasenatmung a test exists. Given various path sensitization criteria, paths are generally classified into several classes: single-path sensitizable, robust, non-robust, functional sensitizable and functional unsensitizable.作者: 形容詞詞尾 時(shí)間: 2025-3-22 19:07
https://doi.org/10.1007/978-3-7091-9947-3ent holds for the functional sensitizable tests. The higher quality non-robust and functional sensitizable tests can be found by including the timing information into the test generation process. This chapter presents test generation algorithms that can produce high quality tests based on using the 作者: absorbed 時(shí)間: 2025-3-22 23:21 作者: Eructation 時(shí)間: 2025-3-23 04:41
Allgemeine Methodik der F?zesuntersuchung“noise faults” such as: distributed delay defects, power bus noise, ground bounce, substrate noise and crosstalk. Analysis shows that excessive noise most of the time leads to delay faults [19]. For example, studies have shown that the increased coupling effects produce interference between signals 作者: triptans 時(shí)間: 2025-3-23 08:08
Book 1998ddition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader‘s understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In 作者: 眉毛 時(shí)間: 2025-3-23 11:39
Introduction, testing has evolved from the common problem faced by the semiconductor industry: designs that function properly at low clock frequencies fail at the rated speed. As experiments show, tests that do not specifically target delay faults have a limited success in detecting timing defects [21, 107, 108,作者: 同謀 時(shí)間: 2025-3-23 14:48
Test Application Schemes for Testing Delay Defects,ed it is necessary to know how these tests will be applied to the circuit. The testing strategy depends on the type of the circuit (combinational, scan, non-scan or partial scan sequential) as well as on the speed of the testing equipment. Ordinarily, testing delay defects requires that the test vec作者: 向前變橢圓 時(shí)間: 2025-3-23 20:27 作者: 遺棄 時(shí)間: 2025-3-24 01:25 作者: 歡樂(lè)中國(guó) 時(shí)間: 2025-3-24 04:25
Delay Fault Simulation,generated fault simulation should be performed to cover as many faults as possible with the same test. Delay fault simulation can also be performed with functional, random, stuck-at or any other available set of vectors to determine the delay fault coverage and reduce the delay test generation effor作者: Obligatory 時(shí)間: 2025-3-24 07:24
Test Generation for Path Delay Faults,robust, validatable non-robust and functional sensitizable faults are considered as single path delay faults. These paths usually can be tested with many different tests, i.e., there are many different robust tests for a robust testable path, many different non-robust tests for a non-robust testable作者: Keshan-disease 時(shí)間: 2025-3-24 12:45
Design for Delay Fault Testability,ably low, most of the research in this area has concentrated on improving the path delay fault testability. Path delay fault testability can be defined with respect to several factors: the number of faults to be tested, the number of tests that need to be applied to test all path delay faults, the n作者: 排名真古怪 時(shí)間: 2025-3-24 16:25 作者: 草率男 時(shí)間: 2025-3-24 21:22
Conclusions and Future Work,in designs in which performance specifications can be violated by very small defects. Studies show that high stuck-at fault coverage is not sufficient to guarantee detection of these timing failures. The use of traditional fault models and testing strategies becomes even more inadequate as the curre作者: jaundiced 時(shí)間: 2025-3-25 01:08
https://doi.org/10.1007/978-3-658-09738-7 testing has evolved from the common problem faced by the semiconductor industry: designs that function properly at low clock frequencies fail at the rated speed. As experiments show, tests that do not specifically target delay faults have a limited success in detecting timing defects [21, 107, 108,作者: adumbrate 時(shí)間: 2025-3-25 03:39 作者: optional 時(shí)間: 2025-3-25 08:57 作者: miniature 時(shí)間: 2025-3-25 15:23
Die Bedeutung der gest?rten Nasenatmungstics. A given path delay fault can be tested by many different tests. Unlike a stuck-at fault for which all tests have the same quality (fault is certainly detected by the test), in path delay fault testing different tests for a given fault have different levels of quality (probability of detection作者: Fecundity 時(shí)間: 2025-3-25 19:38
https://doi.org/10.1007/978-3-7091-9947-3generated fault simulation should be performed to cover as many faults as possible with the same test. Delay fault simulation can also be performed with functional, random, stuck-at or any other available set of vectors to determine the delay fault coverage and reduce the delay test generation effor作者: Aspiration 時(shí)間: 2025-3-25 20:10
https://doi.org/10.1007/978-3-7091-9947-3robust, validatable non-robust and functional sensitizable faults are considered as single path delay faults. These paths usually can be tested with many different tests, i.e., there are many different robust tests for a robust testable path, many different non-robust tests for a non-robust testable作者: 防御 時(shí)間: 2025-3-26 00:16
Das Waschen und Bleichen der Wolleably low, most of the research in this area has concentrated on improving the path delay fault testability. Path delay fault testability can be defined with respect to several factors: the number of faults to be tested, the number of tests that need to be applied to test all path delay faults, the n作者: 感情脆弱 時(shí)間: 2025-3-26 08:17 作者: Incorruptible 時(shí)間: 2025-3-26 10:37
Allgemeine Methodik der F?zesuntersuchungin designs in which performance specifications can be violated by very small defects. Studies show that high stuck-at fault coverage is not sufficient to guarantee detection of these timing failures. The use of traditional fault models and testing strategies becomes even more inadequate as the curre作者: 胰臟 時(shí)間: 2025-3-26 14:32
Frontiers in Electronic Testinghttp://image.papertrans.cn/d/image/264936.jpg作者: 斷言 時(shí)間: 2025-3-26 19:13 作者: 體貼 時(shí)間: 2025-3-26 21:10 作者: 佛刊 時(shí)間: 2025-3-27 03:27 作者: endarterectomy 時(shí)間: 2025-3-27 07:42
Delay Fault Testing for VLSI Circuits978-1-4615-5597-1Series ISSN 0929-1296 作者: 躺下殘殺 時(shí)間: 2025-3-27 13:14 作者: 接合 時(shí)間: 2025-3-27 14:16
https://doi.org/10.1007/978-1-4615-5597-1VLSI; computer-aided design (CAD); design; integrated circuit; modeling; quality; simulation; stability作者: Vasodilation 時(shí)間: 2025-3-27 19:29 作者: 菊花 時(shí)間: 2025-3-27 23:58
0929-1296 gnal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay te作者: 釘牢 時(shí)間: 2025-3-28 05:35 作者: 必死 時(shí)間: 2025-3-28 08:30 作者: 許可 時(shí)間: 2025-3-28 13:55
Die Bedeutung der gest?rten Nasenatmungtors be applied to the circuit at its intended operating speed. However, since high speed testers require huge investments, testers currently used in test facilities could be slower than the new designs that need to be tested on them. Testing high speed designs on slower testers requires special test application and test generation strategies.作者: novelty 時(shí)間: 2025-3-28 14:56 作者: 彎曲道理 時(shí)間: 2025-3-28 20:57
Test Application Schemes for Testing Delay Defects,tors be applied to the circuit at its intended operating speed. However, since high speed testers require huge investments, testers currently used in test facilities could be slower than the new designs that need to be tested on them. Testing high speed designs on slower testers requires special test application and test generation strategies.作者: 消散 時(shí)間: 2025-3-29 00:55
Design for Delay Fault Testability,umber of faults that can be guaranteed to be detected independent of delays outside the target path, etc. This chapter describes design for testability techniques such as test point insertion and use of partial scan as well as techniques for resynthesizing the circuit such that its path delay fault testability is improved.作者: creditor 時(shí)間: 2025-3-29 03:08
Rhinomanometrische Untersuchungene used for representing delay defects lumped at gates while the path and segment delay models address defects that are distributed over several gates. The advantages and disadvantages of each model are discussed.
