作者: Melatonin 時(shí)間: 2025-3-21 21:33 作者: recession 時(shí)間: 2025-3-22 00:53 作者: 發(fā)現(xiàn) 時(shí)間: 2025-3-22 06:07 作者: APEX 時(shí)間: 2025-3-22 10:29
Conference proceedings 2012al support for binary translation; EAMA, the 3rd Workshop for emerging applications and many-core architectures; WEED, 2nd Workshop on energy efficient design, as well as WIOSCA, the annual workshop on the interaction between operating systems and computer architecture..作者: prostate-gland 時(shí)間: 2025-3-22 15:07 作者: prostate-gland 時(shí)間: 2025-3-22 19:13 作者: diskitis 時(shí)間: 2025-3-22 23:50 作者: 乏味 時(shí)間: 2025-3-23 04:50
Taschenbuch für den Maschinenbauformance as a result of early cache miss detection..S-PTC improves average performance from 2.9% to 3.5% for different configurations and for the SPLASH-2 benchmarks used in this study. Our solutions reduce snoop request bandwidth from 78.5% to 81.9% and average tag array dynamic power by about 52%.作者: 微粒 時(shí)間: 2025-3-23 06:16
Implementing a GPU Programming Model on a Non-GPU Accelerator Architecturemprove the performance of CUDA code on a MIMD accelerator architecture that we are developing called Rigel. We demonstrate performance improvements with these optimizations over na?ve translations, and final performance results comparable to those of codes that were hand-optimized for Rigel.作者: 十字架 時(shí)間: 2025-3-23 13:27
Trace Execution Automata in Dynamic Binary Translationore profile information about the generated traces, as well to instrument optimized versions of the traces. In our experiments, we showed that TEA decreases memory needs to represent the traces (nearly 80% savings).作者: 絕緣 時(shí)間: 2025-3-23 13:52 作者: ALB 時(shí)間: 2025-3-23 18:25 作者: modest 時(shí)間: 2025-3-24 01:35
https://doi.org/10.1007/978-3-642-99589-7ove programmability and performance of applications that make heavy use of small convolutions, we argue that two improvements to software and hardware are needed: FFT libraries must be extended with a single convolution function and communication bandwidth between CPU and GPU needs to be drastically improved.作者: 厚臉皮 時(shí)間: 2025-3-24 05:46
Pumpen und Kompressoren verschiedener Bauartottlenecks in future accelerator-based systems we will focus future research on the most performance-critical regions of the design. Accelerator designers will also find our tool useful for selecting which regions of their application to accelerate.作者: 頭腦冷靜 時(shí)間: 2025-3-24 10:30
https://doi.org/10.1007/978-3-642-64925-7ds, our high-end mobile-class system was, on average, 80% more energy-efficient than a cluster with embedded processors and at least 300% more energy-efficient than a cluster with low-power server processors.作者: Painstaking 時(shí)間: 2025-3-24 11:06 作者: 結(jié)合 時(shí)間: 2025-3-24 14:55
On the Use of Small 2D Convolutions on GPUsove programmability and performance of applications that make heavy use of small convolutions, we argue that two improvements to software and hardware are needed: FFT libraries must be extended with a single convolution function and communication bandwidth between CPU and GPU needs to be drastically improved.作者: originality 時(shí)間: 2025-3-24 21:14 作者: craven 時(shí)間: 2025-3-25 00:07
The Search for Energy-Efficient Building Blocks for the Data Centerds, our high-end mobile-class system was, on average, 80% more energy-efficient than a cluster with embedded processors and at least 300% more energy-efficient than a cluster with low-power server processors.作者: foliage 時(shí)間: 2025-3-25 05:53
Achieving Power-Efficiency in Clusters without Distributed File System Complexity DFS design, our solution exploits cluster nodes that have the ability to operate in at least two extreme system level power states, characterized by minimum vs. maximum power consumption and performance. The paper describes a cluster built with power-efficient node prototypes and presents experimental evaluations to demonstrate power-efficiency.作者: Mri485 時(shí)間: 2025-3-25 08:14
Accelerating Agent-Based Ecosystem Models Using the Cell Broadband Engine particle management, which splits and merges agents in order to keep the global agent count within specified bounds. Furthermore, we identify the size of the PPE L2 cache as the main hardware limitation for this process and give an indication of how to perform the required searches more efficiently.作者: defibrillator 時(shí)間: 2025-3-25 14:26
Performance Impact of Task Mapping on the Cell BE Multicore Processorre, we ran exhaustive mapping experiments, and we observed that (1) performance variations can be significant between consecutive runs, and (2) performance forecasts based on intuitive interconnect behavior models are far from accurate even for a simple communication pattern.作者: cumulative 時(shí)間: 2025-3-25 19:12
Can Manycores Support the Memory Requirements of Scientific Applications?aring these requirements with the limitations of state-of-the-art DRAM technology, we project that in the scientific domain, current memory technologies will likely scale well to support more than ~ 100 cores on a single chip, but may become a performance bottleneck for manycores consisting of more than 200 cores.作者: Substitution 時(shí)間: 2025-3-25 20:21 作者: 盡責(zé) 時(shí)間: 2025-3-26 02:57 作者: DECRY 時(shí)間: 2025-3-26 07:12 作者: 災(zāi)難 時(shí)間: 2025-3-26 08:59 作者: 淡紫色花 時(shí)間: 2025-3-26 13:23
Die rotierenden Kraft- und Arbeitsmaschinen unique characteristics that should be considered when selecting a set of benchmarks. Such information can be beneficial for program developers as well as for computer architects who want to understand the behavior of applications.作者: Panacea 時(shí)間: 2025-3-26 19:21 作者: 死亡 時(shí)間: 2025-3-26 22:53
Performance Impact of Task Mapping on the Cell BE Multicore Processorinterconnect is more complex than a bus. We report on our experiments to map a simple application with communication in a ring to SPEs of a Cell BE processor such that performance is optimized. We find that low-level tricks for static mapping do not necessarily achieve optimal performance. Furthermo作者: musicologist 時(shí)間: 2025-3-27 05:11 作者: Mhc-Molecule 時(shí)間: 2025-3-27 07:22
Implementing a GPU Programming Model on a Non-GPU Accelerator Architectureures without significant performance degradation or code rewrites. While . and its limits have been studied thoroughly on single processor systems, this goal has been less extensively studied and is more difficult to achieve for parallel systems. Emerging single-chip parallel platforms are no except作者: ureter 時(shí)間: 2025-3-27 10:39
On the Use of Small 2D Convolutions on GPUslectromagnetic diffraction modeling in physics. The GPU architecture seems to be a suitable architecture to accelerate these convolutions, but reaching high application performance requires substantial development time and non-portable optimizations. In this work, we present the techniques, performa作者: 虛構(gòu)的東西 時(shí)間: 2025-3-27 17:31
Can Manycores Support the Memory Requirements of Scientific Applications?rt such highly parallel processors..In this paper, we examine the memory bandwidth and footprint required by a number of high-performance scientific applications. We find such applications require a per-core memory bandwidth of ~ 300MB/s, and have a memory footprint of some 300MB per-core..When comp作者: 幼兒 時(shí)間: 2025-3-27 19:46
Parallelizing an Index Generator for Desktop Searchon three different Intel platforms with 4, 8, and 32 cores. The optimal configurations for these platforms are not intuitive and are markedly different for the three platforms. For finding the optimal configuration, detailed measurements and experimentation were necessary. Several recommendations fo作者: 草率女 時(shí)間: 2025-3-27 23:31
Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecksctures is a key challenge. In this work, we present a pintool designed to help evaluate the potential benefit of accelerating a particular function. Our tool gathers cross-procedural data usage patterns, including implicit dependencies not captured by arguments and return values. We then use this da作者: 極大的痛苦 時(shí)間: 2025-3-28 05:34
Trace Execution Automata in Dynamic Binary Translationized based on the dynamic information derived from the program’s previous runs. The ability to record traces is thus central to any dynamic binary translation system. Recording traces, as well as loading them for use in different runs, requires code replication to represent the trace. This paper pre作者: hankering 時(shí)間: 2025-3-28 09:25 作者: Extricate 時(shí)間: 2025-3-28 13:49 作者: 證明無罪 時(shí)間: 2025-3-28 15:42
Characteristics of Workloads Using the Pipeline Programming Models of the characteristics of such workloads. This paper gives an overview of the pipeline model and its typical implementations for multiprocessors. We present implementation choices and analyze their impact on the program. We furthermore show that workloads that use the pipeline model have their own作者: Wordlist 時(shí)間: 2025-3-28 20:07 作者: 遺傳 時(shí)間: 2025-3-28 23:01 作者: Malfunction 時(shí)間: 2025-3-29 05:42
Guarded Power Gating in a Multi-core Settingontext, is determining the right balance of gating at the unit-level (within a core) and at the core-level. Another issue is how to architect the predictive control associated with such gating, in order to ensure maximal power savings at minimal performance loss. We use an abstract, analytical model作者: encyclopedia 時(shí)間: 2025-3-29 07:37
Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessorshe observation that detecting tag mismatches in a snoop-based chip multiprocessor does not require aggressively processing the entire tag. In fact, a high percentage of cache mismatches could be detected by utilizing a small subset but highly informative portion of the tag bits..Based on this, we in作者: Thyroxine 時(shí)間: 2025-3-29 15:27
Achieving Power-Efficiency in Clusters without Distributed File System Complexity nodes to achieve power-proportionality, but this leads to problems with availability and fault tolerance because of the resulting limits imposed on the replication strategies used by the distributed file systems (DFS) employed in these environments, with counter-measures adding substantial complexi作者: Negligible 時(shí)間: 2025-3-29 17:53
0302-9743 applications and many-core architectures; WEED, 2nd Workshop on energy efficient design, as well as WIOSCA, the annual workshop on the interaction between operating systems and computer architecture..978-3-642-24321-9978-3-642-24322-6Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: theta-waves 時(shí)間: 2025-3-29 22:16
Taschenbuch für den Fabrikbetriebgramming models is as urgent as ever..This paper presents our first steps in the direction of obtaining a user transparent programming model for data parallel and hierarchical multimedia computing on GPU-clusters. The model is obtained by extending an existing user transparent parallel programming s作者: 偽造者 時(shí)間: 2025-3-30 03:25 作者: grotto 時(shí)間: 2025-3-30 08:06
Pumpen und Kompressoren verschiedener Bauart KnightShift responsibility. We use several production datacenter traces to evaluate the energy impact of KnightShift and show that energy consumption can be reduced by 2.6X by allowing management processors to handle only those requests that demand less than 5% of the primary CPU utilization.作者: Paradox 時(shí)間: 2025-3-30 10:18
Towards User Transparent Parallel Multimedia Computing on GPU-Clustersgramming models is as urgent as ever..This paper presents our first steps in the direction of obtaining a user transparent programming model for data parallel and hierarchical multimedia computing on GPU-clusters. The model is obtained by extending an existing user transparent parallel programming s作者: Saline 時(shí)間: 2025-3-30 14:52 作者: 懲罰 時(shí)間: 2025-3-30 18:22 作者: invulnerable 時(shí)間: 2025-3-30 22:48
Taschenbuch für den Fabrikbetriebodels generated from a domain-specific model compiler called the Virtual Ecology Workbench (VEW). We show that excellent speed-ups over a conventional x86 platform can be achieved for the agent update loop. We also show that scalability of the application as a whole is limited by the need to perform作者: 改變立場(chǎng) 時(shí)間: 2025-3-31 02:18
Heizung, Lüftung, Entstaubung, Beleuchtunginterconnect is more complex than a bus. We report on our experiments to map a simple application with communication in a ring to SPEs of a Cell BE processor such that performance is optimized. We find that low-level tricks for static mapping do not necessarily achieve optimal performance. Furthermo作者: Triglyceride 時(shí)間: 2025-3-31 06:13
Taschenbuch für den Fabrikbetriebta streams. To satisfy the increasing computational demands of MMCA problems, the use of High Performance Computing (HPC) techniques is essential. As most MMCA researchers are not HPC experts, there is an urgent need for ‘familiar’ programming models and tools that are both easy to use and efficient作者: harpsichord 時(shí)間: 2025-3-31 11:56 作者: Estrogen 時(shí)間: 2025-3-31 13:22 作者: BRIDE 時(shí)間: 2025-3-31 18:31 作者: groggy 時(shí)間: 2025-4-1 01:39
