標題: Titlebook: Computer Aided Verification; 9th International Co Orna Grumberg Conference proceedings 1997 Springer-Verlag Berlin Heidelberg 1997 Hardware [打印本頁] 作者: STH 時間: 2025-3-21 17:52
書目名稱Computer Aided Verification影響因子(影響力)
書目名稱Computer Aided Verification影響因子(影響力)學科排名
書目名稱Computer Aided Verification網絡公開度
書目名稱Computer Aided Verification網絡公開度學科排名
書目名稱Computer Aided Verification被引頻次
書目名稱Computer Aided Verification被引頻次學科排名
書目名稱Computer Aided Verification年度引用
書目名稱Computer Aided Verification年度引用學科排名
書目名稱Computer Aided Verification讀者反饋
書目名稱Computer Aided Verification讀者反饋學科排名
作者: 維持 時間: 2025-3-21 22:02 作者: 有偏見 時間: 2025-3-22 03:03
A compositional rule for hardware design refinement, a library of predefined transformations for which theorems have been previously established. Rather, the approach relies on localizing the refinement steps in such a way that they can be verified efficiently by model checking. Toward this end, a compositional rule is proposed by which each design r作者: THROB 時間: 2025-3-22 06:37
Module checking revisited,ith which the system may interact. Each environment induces a different behavior of the system, and we want all these behaviors to satisfy the requirement. . is an algorithmic method that checks, given an open system (modeled as a finite structure) and a desired requirement (specified by a temporal-作者: nutrition 時間: 2025-3-22 10:44
Using compositional preorders in the verification of sliding window protocol,this is to replace components of a system with smaller ones and verify the required properties from the smaller system. This approach leads to notions of compositional property-preserving equivalences and preorders. Previously we have shown that the NDFD preorder is the weakest preorder which is com作者: Aids209 時間: 2025-3-22 15:11 作者: Aids209 時間: 2025-3-22 21:00
Construction of abstract state graphs with PVS,n a parallel composition of sequential processes and a partition of the state space induced by predicates .., ..., .. on the program variables which defines an abstract state space, we construct an abstract state graph, starting in the abstract initial state. The possible successors of a state are c作者: 老巫婆 時間: 2025-3-22 22:02
Verification of a chemical process leak test procedure,obability of explosions. Both government and internal company standards where employed in creating the initial leak test procedure. Several major faults were discovered by the verification of a logic model of the procedure and equipment using SMV. This paper describes the leak test procedure with it作者: 偏見 時間: 2025-3-23 03:15 作者: overrule 時間: 2025-3-23 06:41 作者: 傳染 時間: 2025-3-23 11:05
Towards a mechanization of cryptographic protocol verification,n process. In the original approach verification uses theorem proving. Here we show that for a wide range of practical situations and properties it is possible to perform the verification on a finite and safe abstract model.作者: oncologist 時間: 2025-3-23 14:03
Efficient model checking using tabled resolution,model checkers. In particular, we present XMC, an XSB-based local model checker for a CCS-like value-passing language and the alternation-free fragment of the modal mu-calculus. XMC is written in under 200 lines of XSB code, which constitute a declarative specification of CCS and the modal mu-calcul作者: 來就得意 時間: 2025-3-23 21:09
Containment of regular languages in non-regular timing diagram languages is decidable,es is a difficult problem known to be undecidable in most general cases. This paper establishes that a class of parametrically constrained timing properties can be verified algorithmically against finite-state systems; alternatively stated containment by a regular language is shown decidable for a c作者: BADGE 時間: 2025-3-24 00:40
An improved reachability analysis method for strongly linear hybrid systems (extended abstract),sion of classical state-space exploration. This approach uses a new operation, based on a cycle analysis in the control graph of the system, for generating sets of reachable states, as well as a powerful representation system for sets of values. The method broadens the range of hybrid systems for wh作者: Optometrist 時間: 2025-3-24 03:42
Some progress in the symbolic verification of timed automata,DD-based extension of KRONOS. We have treated examples originating from timing analysis of asynchronous boolean networks and CMOS circuits with delay uncertainties and the results outperform those obtained by previous implementations of timed automata verification tools.作者: 假設 時間: 2025-3-24 07:13 作者: 沖突 時間: 2025-3-24 12:00 作者: Pde5-Inhibitors 時間: 2025-3-24 15:01
https://doi.org/10.1007/978-1-4614-7324-4 a library of predefined transformations for which theorems have been previously established. Rather, the approach relies on localizing the refinement steps in such a way that they can be verified efficiently by model checking. Toward this end, a compositional rule is proposed by which each design r作者: 鋼筆尖 時間: 2025-3-24 21:14 作者: 小歌劇 時間: 2025-3-25 02:40 作者: 顛簸下上 時間: 2025-3-25 05:08 作者: ETHER 時間: 2025-3-25 10:20
SystemVerilog for Design Second Editionn a parallel composition of sequential processes and a partition of the state space induced by predicates .., ..., .. on the program variables which defines an abstract state space, we construct an abstract state graph, starting in the abstract initial state. The possible successors of a state are c作者: PALSY 時間: 2025-3-25 12:58 作者: 有角 時間: 2025-3-25 16:04
SystemVerilog Declaration Spaces,lued BDDs, which represent functions of the form ., where . is a finite set of leaves..We study a rather natural online BDD refinement problem: a partition of the leaves of several shared BDDs is gradually refined, and the equivalence of the BDDs under the current partition must be maintained in a d作者: 晚間 時間: 2025-3-25 21:18 作者: 注視 時間: 2025-3-26 03:10 作者: myocardium 時間: 2025-3-26 05:06
SystemVerilog Arrays, Structures and Unions,model checkers. In particular, we present XMC, an XSB-based local model checker for a CCS-like value-passing language and the alternation-free fragment of the modal mu-calculus. XMC is written in under 200 lines of XSB code, which constitute a declarative specification of CCS and the modal mu-calcul作者: 陰險 時間: 2025-3-26 11:03
https://doi.org/10.1007/0-387-36495-1es is a difficult problem known to be undecidable in most general cases. This paper establishes that a class of parametrically constrained timing properties can be verified algorithmically against finite-state systems; alternatively stated containment by a regular language is shown decidable for a c作者: infinite 時間: 2025-3-26 13:49
SystemVerilog Design Hierarchy,sion of classical state-space exploration. This approach uses a new operation, based on a cycle analysis in the control graph of the system, for generating sets of reachable states, as well as a powerful representation system for sets of values. The method broadens the range of hybrid systems for wh作者: slow-wave-sleep 時間: 2025-3-26 19:09 作者: Decline 時間: 2025-3-26 21:01
https://doi.org/10.1007/3-540-63166-6Hardware; algorithm; algorithms; computer; formal method; hardware verification; tools; verification作者: Kinetic 時間: 2025-3-27 05:08
978-3-540-63166-8Springer-Verlag Berlin Heidelberg 1997作者: 牛馬之尿 時間: 2025-3-27 06:53 作者: 2否定 時間: 2025-3-27 10:09
SystemVerilog Arrays, Structures and Unions,n process. In the original approach verification uses theorem proving. Here we show that for a wide range of practical situations and properties it is possible to perform the verification on a finite and safe abstract model.作者: Confirm 時間: 2025-3-27 17:41
SystemVerilog for Design Second EditionDD-based extension of KRONOS. We have treated examples originating from timing analysis of asynchronous boolean networks and CMOS circuits with delay uncertainties and the results outperform those obtained by previous implementations of timed automata verification tools.作者: misshapen 時間: 2025-3-27 18:06 作者: 溝通 時間: 2025-3-27 22:28 作者: Isthmus 時間: 2025-3-28 05:12 作者: 賞心悅目 時間: 2025-3-28 09:33
SystemC: From the Ground Up, Second Editionial use, for instance in the areas of telecom service specification analysis, analysis of railway interlocking software, analysis of programmable controllers and analysis of aircraft systems. The method seems suitable also for hardware verification.作者: 編輯才信任 時間: 2025-3-28 12:31 作者: nautical 時間: 2025-3-28 18:11
SystemVerilog for Design Second Editione core bit-vector theory is extended to handle other bit-vector operations like bitwise logical operations, shifting, and arithmetic interpretations of bit-vectors. We develop a BDD-like data-structure called bit-vector BDDs to represent bit-vectors, various operations on bit-vectors, and a solver on bit-vector BDDs.作者: MEET 時間: 2025-3-28 20:09
,The industrial success of verification tools based on st?lmarck’s method,ial use, for instance in the areas of telecom service specification analysis, analysis of railway interlocking software, analysis of programmable controllers and analysis of aircraft systems. The method seems suitable also for hardware verification.作者: chisel 時間: 2025-3-29 01:00
Using compositional preorders in the verification of sliding window protocol,reorder was used to verify semiautomatically both safety and liveness properties of the Sliding Window protocol for arbitrary channel lengths and realistic parameter values. In this process we located a previously undiscovered fault leading to lack of liveness in a version of the protocol.作者: 鎮(zhèn)痛劑 時間: 2025-3-29 05:55
An efficient decision procedure for the theory of fixed-sized bit-vectors,e core bit-vector theory is extended to handle other bit-vector operations like bitwise logical operations, shifting, and arithmetic interpretations of bit-vectors. We develop a BDD-like data-structure called bit-vector BDDs to represent bit-vectors, various operations on bit-vectors, and a solver on bit-vector BDDs.作者: Encapsulate 時間: 2025-3-29 09:49
0302-9743 Haifa, Israel, in June 1997..The volume presents 34 revised full papers selected from a total of 84 submissions. Also included are 7 invited contributions as well as 12 tool descriptions. The volume is dedicated to the theory and practice of computer aided formal methods for software and hardware v作者: hidebound 時間: 2025-3-29 11:29 作者: 使虛弱 時間: 2025-3-29 19:02
https://doi.org/10.1007/0-387-36495-1erties can be verified algorithmically against finite-state systems; alternatively stated containment by a regular language is shown decidable for a class of language properties (regular and non-regular) expressible in our timing diagram logic.作者: padding 時間: 2025-3-29 21:34 作者: ROOF 時間: 2025-3-30 00:12
Containment of regular languages in non-regular timing diagram languages is decidable,erties can be verified algorithmically against finite-state systems; alternatively stated containment by a regular language is shown decidable for a class of language properties (regular and non-regular) expressible in our timing diagram logic.作者: 造反,叛亂 時間: 2025-3-30 06:28
SystemVerilog Declaration Spaces,how that automata with BDD-represented transition functions can be minimized in time .(.·log .), where . is the total number of BDD nodes representing the automaton. This result is not an instance of Hopcroft‘s classical algorithm for automaton minimization, which breaks down for BDDs because of their path compression property.作者: micronized 時間: 2025-3-30 09:02
SystemVerilog Arrays, Structures and Unions,cation and verification environments. After applying certain newly developed logic-programming-based optimizations (along with some standard ones), XMC‘s performance became extremely competitive with that of the Factory and shows promise in its comparison with SPIN.作者: hair-bulb 時間: 2025-3-30 16:21 作者: MUTE 時間: 2025-3-30 19:23 作者: 歸功于 時間: 2025-3-30 21:59 作者: 瑣碎 時間: 2025-3-31 02:42
Conference proceedings 1997ell as 12 tool descriptions. The volume is dedicated to the theory and practice of computer aided formal methods for software and hardware verification, with an emphasis on verification tools and algorithms and the techniques needed for their implementation. The book is a unique record documenting the recent progress in the area.作者: Ganglion 時間: 2025-3-31 07:54 作者: 樹上結蜜糖 時間: 2025-3-31 11:31
https://doi.org/10.1007/978-1-4614-7324-4efinement may be verified independently, in an abstract environment. This rule supports the use of downward refinement maps, which translate abstract behavior detailed behavior. These maps may involve temporal transformations, including delay. The approach is supported by a verification tool based on symbolic model checking.作者: CANDY 時間: 2025-3-31 13:43 作者: 不能逃避 時間: 2025-3-31 20:54 作者: Brain-Imaging 時間: 2025-3-31 21:43
SystemVerilog Design Hierarchy,ich a finite and exact representation of the set of reachable states can be computed. In particular, the state-space exploration may be performed even if the set of variable values reachable at a given control location cannot be expressed as a finite union of convex regions. The technique is illustrated on a very simple example.作者: 即席演說 時間: 2025-4-1 04:41
Automatic abstraction techniques for propositional ,-calculus model checking,re further resolution. It then successively refines, with respect to this goal set, the approximations made in the subformulas, until the given formula is verified or computational resources are exhausted.作者: 殘酷的地方 時間: 2025-4-1 08:04
A compositional rule for hardware design refinement,efinement may be verified independently, in an abstract environment. This rule supports the use of downward refinement maps, which translate abstract behavior detailed behavior. These maps may involve temporal transformations, including delay. The approach is supported by a verification tool based on symbolic model checking.作者: LIEN 時間: 2025-4-1 10:42 作者: ALIAS 時間: 2025-4-1 17:03 作者: 窒息 時間: 2025-4-1 19:02 作者: 注入 時間: 2025-4-1 23:03
0302-9743 erification, with an emphasis on verification tools and algorithms and the techniques needed for their implementation. The book is a unique record documenting the recent progress in the area.978-3-540-63166-8978-3-540-69195-2Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: 闖入 時間: 2025-4-2 05:24
