標(biāo)題: Titlebook: Circuit and Interconnect Design for RF and High Bit-rate Applications; Hugo Veenstra,John R. Long Book 20081st edition Springer Science+Bu [打印本頁] 作者: Racket 時間: 2025-3-21 17:10
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書目名稱Circuit and Interconnect Design for RF and High Bit-rate Applications讀者反饋學(xué)科排名
作者: Lipoprotein 時間: 2025-3-22 00:09 作者: VEIL 時間: 2025-3-22 04:14 作者: 愛了嗎 時間: 2025-3-22 06:27 作者: Gene408 時間: 2025-3-22 10:59 作者: cunning 時間: 2025-3-22 14:45
Aniceto C. Orbeta Jr,Maria Teresa C. Sancheztical networks. The switch matrix, which forms the core of the cross-connect switch IC, is an excellent example showing that optimum performance can only be obtained when circuits and interconnect are optimised together. For the design and optimisation of the signal distribution inside the matrix, e作者: cunning 時間: 2025-3-22 19:39 作者: hysterectomy 時間: 2025-3-22 23:34
International Political Economy Seriestarget is to achieve an output bit-rate of at least 40 Gb/s. Detailed circuit simulations using the SiGe technology also used for the 12.5 Gb/s cross-connect switch described in Chapter 4 revealed that a clock to data delay of approximately 15 ps per latch allows the design of a half-rate PRBS core.作者: rods366 時間: 2025-3-23 01:27 作者: COM 時間: 2025-3-23 07:27 作者: 斜坡 時間: 2025-3-23 12:34
https://doi.org/10.1007/978-1-4020-6884-3Avalanche Multiplication; CMOS; Circuit Design; Cross-Connect Switch; Device Metrics; Distributed Capacit作者: 徹底明白 時間: 2025-3-23 16:14
978-90-481-7750-9Springer Science+Business Media B.V. 2008作者: CYN 時間: 2025-3-23 21:36 作者: 想象 時間: 2025-3-24 00:17 作者: Ointment 時間: 2025-3-24 06:11
Thailand in the Regional Division of Labourcan be increased by employing double emitter followers in the RF signal path. However, to be able to do so, the supply voltage must be increased to a value above the collector-emitter breakdown voltage (BVCEO) of the high-speed transistors of the technology.作者: tinnitus 時間: 2025-3-24 07:59
Bias Circuits Tolerating Output Voltages Above BVCEO,can be increased by employing double emitter followers in the RF signal path. However, to be able to do so, the supply voltage must be increased to a value above the collector-emitter breakdown voltage (BVCEO) of the high-speed transistors of the technology.作者: 音樂等 時間: 2025-3-24 13:29 作者: Oligarchy 時間: 2025-3-24 18:30 作者: parsimony 時間: 2025-3-24 20:46
Circuit and Interconnect Design for RF and High Bit-rate Applications作者: anesthesia 時間: 2025-3-24 23:24
Book 20081st editionthe effects of interconnections as soon as estimated interconnect lengths are available. Application of interconnect design is illustrated using a 12.5 Gb/s crosspoint switch example taken from a volume production part.作者: OVERT 時間: 2025-3-25 03:35
https://doi.org/10.1007/978-1-349-25931-1rk capacity is being increased by two technologies simultaneously. One is higher data processing speeds and electronic time division multiplexing (ETDM), which drives the increase of bit-rates. The second is wavelength division multiplexing (WDM), which allows the use of multiple independent data st作者: Vulvodynia 時間: 2025-3-25 07:38 作者: 不透明性 時間: 2025-3-25 12:30
Aniceto C. Orbeta Jr,Maria Teresa C. Sanchez rates up to 12.5 Gb/s per input. The block diagram of the switch IC is shown in Fig. 1.9. An overview of the main specifications is provided in Table 4.1..The main focus of this chapter is on the design of the RF signal path. The IC is designed for wire bonding, so all the bondpads must be located 作者: 態(tài)學(xué) 時間: 2025-3-25 15:56
International Political Economy Serieschnology are very similar, as will be demonstrated in this chapter..The maximum speed of digital circuits in a given IC process is often benchmarked on the basis of minimum gate delays, obtained from a ring oscillator. Such a ring oscillator can be built from simple inverters and therefore provides 作者: Expertise 時間: 2025-3-25 21:23
https://doi.org/10.1057/9780333977927beyond .. in bipolar circuit implementations)..Many tuneable LC oscillators apply a cross-coupled differential pair to undamp the LC-tank circuit, leading to the basic configuration shown in Fig. 7.1.作者: GRUEL 時間: 2025-3-26 04:07 作者: Pepsin 時間: 2025-3-26 04:46
The Challenge,rk capacity is being increased by two technologies simultaneously. One is higher data processing speeds and electronic time division multiplexing (ETDM), which drives the increase of bit-rates. The second is wavelength division multiplexing (WDM), which allows the use of multiple independent data st作者: Meditate 時間: 2025-3-26 10:08
Interconnect Modelling, Analysis and Design,owest possible impedance is required for the ground path. Different implementations for the ground path exist, such as a wire, a set of wires connected in parallel, a mesh, a plane, or a combination of these..In this book, the multi-section RLC model is also referred to as a transmission line model.作者: lymphedema 時間: 2025-3-26 13:21 作者: 把手 時間: 2025-3-26 20:35 作者: 情感 時間: 2025-3-27 00:57 作者: slow-wave-sleep 時間: 2025-3-27 04:37 作者: 骨 時間: 2025-3-27 05:17 作者: AIL 時間: 2025-3-27 10:42
Device Metrics,hnology parameters one can predict the impact of a new technology on applications. This chapter reviews device metrics that will be used for circuit design in the rest of this book. The metric that is most widely used for the evaluation of an IC process is .., representing the transition frequency o作者: Foolproof 時間: 2025-3-27 13:56
Cross-Connect Switch Design,tical networks. The switch matrix, which forms the core of the cross-connect switch IC, is an excellent example showing that optimum performance can only be obtained when circuits and interconnect are optimised together. For the design and optimisation of the signal distribution inside the matrix, e作者: hair-bulb 時間: 2025-3-27 18:47 作者: progestogen 時間: 2025-3-28 00:09
Design of Synchronous High-Speed CML Circuits, a PRBS Generator,target is to achieve an output bit-rate of at least 40 Gb/s. Detailed circuit simulations using the SiGe technology also used for the 12.5 Gb/s cross-connect switch described in Chapter 4 revealed that a clock to data delay of approximately 15 ps per latch allows the design of a half-rate PRBS core.作者: Insufficient 時間: 2025-3-28 03:03 作者: Guaff豪情痛飲 時間: 2025-3-28 06:54
Theories on intrafamily time allocation,ithin a household setting. It was labor economist Jacob Mincer (1962) who first pointed out the importance of distinguishing between the times uses of market work, non-market work and leisure. The first systematic approach to a general theory of the allocation of time was made by Gary S. Becker (196作者: prosthesis 時間: 2025-3-28 11:41 作者: 結(jié)果 時間: 2025-3-28 14:58
,Electric Axle Drives – scalable propulsion system for electrified powertrains,lektrischen Antrieb wurde ebenfalls ein skalierbares Modulkonzept entwickelt. Neben Magnetkreisen unterschiedlicher Technologie wurden für die Leistungselektronik Baugruppen definiert, die die hohen Anforderungen an Zyklenfestigkeit, Leistungsdichte und Robustheit in Bezug auf die Umgebungsbedingung
