標題: Titlebook: Architecture of High Performance Computers; Volume I: Uniprocess R. N. Ibbett,N. P. Topham Textbook 1989Latest edition Roland N. Ibbett and [打印本頁] 作者: 恐怖 時間: 2025-3-21 20:03
書目名稱Architecture of High Performance Computers影響因子(影響力)
書目名稱Architecture of High Performance Computers影響因子(影響力)學科排名
書目名稱Architecture of High Performance Computers網(wǎng)絡(luò)公開度
書目名稱Architecture of High Performance Computers網(wǎng)絡(luò)公開度學科排名
書目名稱Architecture of High Performance Computers被引頻次
書目名稱Architecture of High Performance Computers被引頻次學科排名
書目名稱Architecture of High Performance Computers年度引用
書目名稱Architecture of High Performance Computers年度引用學科排名
書目名稱Architecture of High Performance Computers讀者反饋
書目名稱Architecture of High Performance Computers讀者反饋學科排名
作者: 刺激 時間: 2025-3-21 20:14
Introduction,n be organised so as to maximise performance, as measured by, for example, average instruction execution time. Thus the architect of a high performance system seeks techniques whereby judicious use of increased cost and complexity in the hardware will give a significant increase in overall system performance.作者: 變異 時間: 2025-3-22 02:05 作者: 懶惰人民 時間: 2025-3-22 08:23 作者: hazard 時間: 2025-3-22 09:33 作者: 確定方向 時間: 2025-3-22 16:09 作者: Inertia 時間: 2025-3-22 18:53 作者: 薄膜 時間: 2025-3-23 00:43
https://doi.org/10.1007/978-1-349-19757-6architecture; architectures; computer; function; performance; processor; storage; techniques; Volume作者: periodontitis 時間: 2025-3-23 02:41
Roland N. Ibbett and Nigel P. Topham 1989作者: N斯巴達人 時間: 2025-3-23 07:03 作者: accordance 時間: 2025-3-23 09:50 作者: Preserve 時間: 2025-3-23 17:45 作者: Ferritin 時間: 2025-3-23 20:29
Studies in Computational Intelligencetation, operand accessing and arithmetic. If separate hardware units carry out these activities their operations can be overlapped to give an increased rate of completion of instructions. This technique, first introduced in computers such as Atlas and Stretch, has become known as . In a pipelined co作者: Fraudulent 時間: 2025-3-23 23:12
Evolutionary Search and the Job Shopn store accessing rate. This problem also impinges on instruction accessing, since for efficient operation instructions must also be supplied to the processor at a rate matching its execution rate. In the case of instruction accessing, however, the problem is ameliorated by the fact that most instru作者: Ptsd429 時間: 2025-3-24 04:37
Evolutionary Search and the Job Shopas a means of enhancing the performance of a processor at the top end of a range of general purpose computers. In the case of the CDC 6600, performance was the principal criterion of the design, and as we saw in chapter 2, the use of parallel functional units with an instruction set capable of explo作者: 就職 時間: 2025-3-24 08:41
https://doi.org/10.1007/978-1-4020-8215-3eumann concept, for example, included the notion of allowing instructions to be treated as data, which meant that the address part of an instruction accessing a vector element could be incremented during the execution of a program loop and thus produce the effect of processing a vector. In practice,作者: 山頂可休息 時間: 2025-3-24 12:27
https://doi.org/10.1007/978-1-4020-8215-3support in hardware for the management of data structures. Thus a data structure as seen by the programmer is broken up into small sections and mapped into the vector registers by software. In machines which process the programmer’s data structures more directly, a number of quite different problems作者: 災(zāi)難 時間: 2025-3-24 15:52 作者: obsession 時間: 2025-3-24 20:30
https://doi.org/10.1007/978-3-642-16218-3d in memory, whereas the other, the CRAY family, uses operands held in vector registers. Knowledge about such aspects of their design, together with knowledge about the clock periods of these machines, provides a limited picture of their performance potential. For example, before spending several mi作者: 陳列 時間: 2025-3-25 01:35
Instructions and Addresses,dated in one instruction. On the other hand, where full store addresses are used, multiple-address instructions are generally regarded as prohibitively expensive both in terms of machine complexity and in terms of the static and dynamic code requirements. Thus one store address per instruction is us作者: optic-nerve 時間: 2025-3-25 04:55 作者: defeatist 時間: 2025-3-25 08:57
Pipelines,rinciple has been extended to several tens of instructions and used in both arithmetic and instruction processing units. In this chapter we shall discuss the principles of pipeline design, and then consider the actual design of the MU5 Primary Operand Unit as an example of instruction pipelining and作者: definition 時間: 2025-3-25 11:47
Instruction Buffers, execution. This . technique is used in almost all high performance pipelined processors. A significant proportion of instructions cause control transfers, however, and each such transfer requires a request to be made to the store for a new sequence of instructions. Thus although the accessing rate 作者: Preamble 時間: 2025-3-25 18:16 作者: 小說 時間: 2025-3-25 21:06 作者: 先行 時間: 2025-3-26 01:45 作者: 單調(diào)女 時間: 2025-3-26 06:54
Lecture Notes in Computer Sciencedated in one instruction. On the other hand, where full store addresses are used, multiple-address instructions are generally regarded as prohibitively expensive both in terms of machine complexity and in terms of the static and dynamic code requirements. Thus one store address per instruction is us作者: 2否定 時間: 2025-3-26 09:38
First Three Generations of Evolved Robots,echnology led to the need for more sophisticated systems and in this chapter we shall consider the virtual memory and paging systems used in Atlas, the cache stores used in some models in the IBM System/360 and System/370 ranges, and the MU5 storage hierarchy. Before discussing these systems in deta作者: 懸崖 時間: 2025-3-26 14:45
Studies in Computational Intelligencerinciple has been extended to several tens of instructions and used in both arithmetic and instruction processing units. In this chapter we shall discuss the principles of pipeline design, and then consider the actual design of the MU5 Primary Operand Unit as an example of instruction pipelining and作者: 表示問 時間: 2025-3-26 20:48 作者: 無能力 時間: 2025-3-26 22:13 作者: medium 時間: 2025-3-27 03:31 作者: Intrepid 時間: 2025-3-27 07:41
https://doi.org/10.1007/978-3-642-16218-3 is analysed it is useful to separate the architectural measurements from the technological measurements since this permits a comparison of the . of machines constructed from different technologies. This chapter therefore considers the ways in which the performance potential of vector processors can作者: concubine 時間: 2025-3-27 10:35 作者: 角斗士 時間: 2025-3-27 15:45 作者: Reclaim 時間: 2025-3-27 21:39 作者: 要控制 時間: 2025-3-28 00:12
Pipelines,tation, operand accessing and arithmetic. If separate hardware units carry out these activities their operations can be overlapped to give an increased rate of completion of instructions. This technique, first introduced in computers such as Atlas and Stretch, has become known as . In a pipelined co作者: 飛來飛去真休 時間: 2025-3-28 02:47
Instruction Buffers,n store accessing rate. This problem also impinges on instruction accessing, since for efficient operation instructions must also be supplied to the processor at a rate matching its execution rate. In the case of instruction accessing, however, the problem is ameliorated by the fact that most instru作者: 苦笑 時間: 2025-3-28 09:38
Parallel Functional Units,as a means of enhancing the performance of a processor at the top end of a range of general purpose computers. In the case of the CDC 6600, performance was the principal criterion of the design, and as we saw in chapter 2, the use of parallel functional units with an instruction set capable of explo作者: Rejuvenate 時間: 2025-3-28 13:40 作者: Cerumen 時間: 2025-3-28 16:48
Vector Facilities in MU5,support in hardware for the management of data structures. Thus a data structure as seen by the programmer is broken up into small sections and mapped into the vector registers by software. In machines which process the programmer’s data structures more directly, a number of quite different problems作者: 亂砍 時間: 2025-3-28 21:29 作者: 寄生蟲 時間: 2025-3-28 23:23
Performance of Vector Machines,d in memory, whereas the other, the CRAY family, uses operands held in vector registers. Knowledge about such aspects of their design, together with knowledge about the clock periods of these machines, provides a limited picture of their performance potential. For example, before spending several mi作者: Induction 時間: 2025-3-29 06:28
From Deforestation to Reforestation in New England, United Statespoints raise the possibility that current land-use analysis may lack future policy relevance. Also, these processes suggest mechanisms through which forested area might first drop and then rise with development. However, in New England the sign reversal in the change in forest area depended at least作者: 是貪求 時間: 2025-3-29 11:11
Biografie – Bilder – Adressierungene field of the horseshoe magnet; a spiral spring opposes this movement, and the coil will set in some intermediate position. A pointer is attached to the coil and moves over a scale marked in divisions.作者: Incorporate 時間: 2025-3-29 12:02 作者: 一小塊 時間: 2025-3-29 15:45
