標(biāo)題: Titlebook: Architecture of Computing Systems – ARCS 2018; 31st International C Mladen Berekovic,Rainer Buchty,Thilo Pionteck Conference proceedings 20 [打印本頁] 作者: cerebral-cortex 時(shí)間: 2025-3-21 18:42
書目名稱Architecture of Computing Systems – ARCS 2018影響因子(影響力)
書目名稱Architecture of Computing Systems – ARCS 2018影響因子(影響力)學(xué)科排名
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書目名稱Architecture of Computing Systems – ARCS 2018網(wǎng)絡(luò)公開度學(xué)科排名
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書目名稱Architecture of Computing Systems – ARCS 2018被引頻次學(xué)科排名
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書目名稱Architecture of Computing Systems – ARCS 2018年度引用學(xué)科排名
書目名稱Architecture of Computing Systems – ARCS 2018讀者反饋
書目名稱Architecture of Computing Systems – ARCS 2018讀者反饋學(xué)科排名
作者: SHOCK 時(shí)間: 2025-3-21 23:17
Jeffrey A. Joines,Michael G. Kay: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedicated hardware, usually as a state machine or a combination of communicating state machines, these functionalities may also be implemented by a small proce作者: 態(tài)度暖昧 時(shí)間: 2025-3-22 01:34 作者: 苦笑 時(shí)間: 2025-3-22 06:13
Jeffrey A. Joines,Michael G. Kayy or the high Worst Case Execution Time (WCET) overestimation caused by the use of shared resources. Nevertheless, multicore processors can significantly increase system integration density also in critical and hard real-time applications..We present a Closed Performance Control Loop that enables a 作者: 盤旋 時(shí)間: 2025-3-22 12:02 作者: 廚師 時(shí)間: 2025-3-22 13:19 作者: fastness 時(shí)間: 2025-3-22 19:54
https://doi.org/10.1007/978-94-017-9520-3uating the different processor cores regarding their runtime for a certain algorithm requires simulation tools which make emulation feasible. They come in two flavors: Cycle and instruction accurate simulation. The first one offers a high accuracy regarding the estimated time but is very slow. The s作者: 使熄滅 時(shí)間: 2025-3-22 23:12 作者: 效果 時(shí)間: 2025-3-23 01:37 作者: 心神不寧 時(shí)間: 2025-3-23 07:51 作者: BADGE 時(shí)間: 2025-3-23 13:45 作者: Flounder 時(shí)間: 2025-3-23 14:59
Kathrin Dudenh?ffer,Leonie Hausethe different cores are not cycle synchronous. Furthermore, current and future safety-critical applications demand fail-operational execution, which requires mechanisms for error recovery..In this paper, we propose a loosely-coupled redundancy approach which combines an in-order with an out-of-order作者: Insensate 時(shí)間: 2025-3-23 19:57
Richard Colmorn,Michael Hülsmann area and power consumption. In this paper, we consider an emerging non volatile memory technology, namely the Spin-Transfer Torque Magnetic RAM (STT-MRAM), with a powerful cache replacement policy in order to design an efficient STT-MRAM Last-Level Cache (LLC) in terms of performance. Well-known be作者: Aboveboard 時(shí)間: 2025-3-23 22:57 作者: 烤架 時(shí)間: 2025-3-24 06:21
Lecture Notes in Computer Sciencehttp://image.papertrans.cn/b/image/161318.jpg作者: 中和 時(shí)間: 2025-3-24 09:00 作者: dragon 時(shí)間: 2025-3-24 13:39 作者: –DOX 時(shí)間: 2025-3-24 16:34
Architecture of Computing Systems – ARCS 2018978-3-319-77610-1Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: adhesive 時(shí)間: 2025-3-24 20:19
Constrained Evolutionary Optimization phenomena. Our result is that scalability across fields can be interpreted as a tradeoff in three dimensions between too competitive and too cooperative processing schemes, too little information sharing and too much information sharing, while finding a balance between neither underusing nor deplet作者: GRAZE 時(shí)間: 2025-3-25 00:01 作者: 愉快么 時(shí)間: 2025-3-25 07:14
Why yet another one evolutionary optimizer?,constraints of safety-critical traffic..The results thus obtained are then compared with a capacity-constrained and an Earliest-Deadline-First placement heuristic. Hence it can be shown that while heuristics can perform well in some aspects, they violate either capacity or timing constraints, thus m作者: 六邊形 時(shí)間: 2025-3-25 11:04
Superlinear Scalability in Parallel Computing and Multi-robot Systems: Shared Resources, Collaborati phenomena. Our result is that scalability across fields can be interpreted as a tradeoff in three dimensions between too competitive and too cooperative processing schemes, too little information sharing and too much information sharing, while finding a balance between neither underusing nor deplet作者: liaison 時(shí)間: 2025-3-25 14:11 作者: arthrodesis 時(shí)間: 2025-3-25 19:16
Network Optimization for Safety-Critical Systems Using Software-Defined Networksconstraints of safety-critical traffic..The results thus obtained are then compared with a capacity-constrained and an Earliest-Deadline-First placement heuristic. Hence it can be shown that while heuristics can perform well in some aspects, they violate either capacity or timing constraints, thus m作者: judiciousness 時(shí)間: 2025-3-25 22:03 作者: 發(fā)怨言 時(shí)間: 2025-3-26 00:09 作者: 防止 時(shí)間: 2025-3-26 04:38 作者: 憤慨一下 時(shí)間: 2025-3-26 09:57 作者: aqueduct 時(shí)間: 2025-3-26 15:41 作者: Abrupt 時(shí)間: 2025-3-26 17:39
Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodeseen resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GP作者: Demonstrate 時(shí)間: 2025-3-26 21:33
A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Modeluating the different processor cores regarding their runtime for a certain algorithm requires simulation tools which make emulation feasible. They come in two flavors: Cycle and instruction accurate simulation. The first one offers a high accuracy regarding the estimated time but is very slow. The s作者: dyspareunia 時(shí)間: 2025-3-27 04:10
A CAM-Free Exascalable HPC Router for?Low-Energy Communicationselements. While this problem is being addressed by designing increasingly more power-efficient processing subsystems, little effort has been put on reducing the power consumption of the interconnection network. This is precisely the objective of this work, in which we study the benefits, in terms of作者: 異端 時(shí)間: 2025-3-27 06:15 作者: arrogant 時(shí)間: 2025-3-27 13:15 作者: ear-canal 時(shí)間: 2025-3-27 15:46 作者: 辯論 時(shí)間: 2025-3-27 21:17 作者: 現(xiàn)存 時(shí)間: 2025-3-28 00:04
Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy area and power consumption. In this paper, we consider an emerging non volatile memory technology, namely the Spin-Transfer Torque Magnetic RAM (STT-MRAM), with a powerful cache replacement policy in order to design an efficient STT-MRAM Last-Level Cache (LLC) in terms of performance. Well-known be作者: Tortuous 時(shí)間: 2025-3-28 05:58 作者: 滔滔不絕地講 時(shí)間: 2025-3-28 06:18
Conference proceedings 2018any, in April 2018..The 23 full papers presented in this volume were carefully reviewed and selected from 53 submissions. ARCS has always been a conference?attracting leading-edge research outcomes in Computer Architecture and Operating?Systems, including a wide spectrum of topics ranging from embed作者: SEEK 時(shí)間: 2025-3-28 12:50
A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Modelecond one offers a high simulation speed but only provides a very imprecise estimation of the real runtime. This paper shows a new approach that allows to combine these kinds of simulation to increase the exactness of the estimated time while limiting the additionally required simulation time.作者: 固執(zhí)點(diǎn)好 時(shí)間: 2025-3-28 17:55
CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore Platformsadvantages (no retries and lock-free) of both variants by using dedicated hardware support for inter-tile atomic operations. For frequently used and highly concurrent data structures, we show a speedup factor of 23.9 and 35.4 over the lock-based and lock-free implementations respectively, which increases with higher concurrency.作者: 愛花花兒憤怒 時(shí)間: 2025-3-28 21:25
0302-9743 weig, Germany, in April 2018..The 23 full papers presented in this volume were carefully reviewed and selected from 53 submissions. ARCS has always been a conference?attracting leading-edge research outcomes in Computer Architecture and Operating?Systems, including a wide spectrum of topics ranging 作者: 起波瀾 時(shí)間: 2025-3-29 00:29
Jeffrey A. Joines,Michael G. Kay hardware, usually as a state machine or a combination of communicating state machines, these functionalities may also be implemented by a small processor. In this paper, we present Lipsi, a very tiny processor to make it possible to implement classic finite state machine logic in software at a minimal cost.作者: Contort 時(shí)間: 2025-3-29 07:10
Richard Colmorn,Michael Hülsmann new profiling techniques based on the automatic classification of program allocation sites, with the goal of using those classifications to guide memory tier assignments. We evaluate our approach with different profiling inputs and application strategies, and show that it outperforms other state-of-the-art management techniques.作者: 尊敬 時(shí)間: 2025-3-29 09:39 作者: Asparagus 時(shí)間: 2025-3-29 14:29
On Automated Feedback-Driven Data Placement in Multi-tiered Memory new profiling techniques based on the automatic classification of program allocation sites, with the goal of using those classifications to guide memory tier assignments. We evaluate our approach with different profiling inputs and application strategies, and show that it outperforms other state-of-the-art management techniques.作者: CRUDE 時(shí)間: 2025-3-29 17:07 作者: 逗它小傻瓜 時(shí)間: 2025-3-29 23:02 作者: faddish 時(shí)間: 2025-3-30 00:10
Closed Loop Controller for Multicore Real-Time Systemstional software functionality on the multicore is required. The previously presented Fingerprinting approach to measure an application’s performance is used as sensor element, extended by a Pulse Width Modulated core thwarting technique and two different control algorithms are combined to a Closed Control Loop.作者: 思想流動(dòng) 時(shí)間: 2025-3-30 04:07
Redundant Execution on Heterogeneous Multi-cores Utilizing Transactional Memorynism is leveraged to recover from errors. The resulting system runs up to 2.9 times faster than a lockstep system consisting of two in-order cores and consumes up to 35% less energy at the same performance than a lockstep system consisting of two out-of-order cores.作者: ANTE 時(shí)間: 2025-3-30 11:43
Ruhul Sarker,Carlos A. Coello Coello defined schedules, in which the user can give their preferences about the trade-off between performance, energy and fault tolerance. We present an approach for determining the best trade-off for modern multicore architectures and we test RUPS on a real system to verify the accuracy of our approach itself.作者: Cerebrovascular 時(shí)間: 2025-3-30 14:21 作者: 思考而得 時(shí)間: 2025-3-30 17:08 作者: 協(xié)議 時(shí)間: 2025-3-30 23:43
https://doi.org/10.1007/978-1-4615-0911-0 controlling our hardware supported synchronization, we add two new assembler instructions. Furthermore, we show the difference in the software development process and evaluate the impact on the execution time of global communication operations and required receive buffer slots.作者: 灰心喪氣 時(shí)間: 2025-3-31 03:05
Richard Colmorn,Michael Hülsmannmental to system performance. In order to mitigate this issue, we combine STT-MRAM with a recent cache The benefit of this combination is evaluated through experiments on SPEC CPU2006 benchmark suite, showing performance improvements of up?to 10% compared to SRAM cache with LRU on a single core system.
