標(biāo)題: Titlebook: Application Specific Processors; Earl E. Swartzlander Book 1997 Kluwer Academic Publishers 1997 ASIC.CMOS.Computer.algorithms.development. [打印本頁(yè)] 作者: CHARY 時(shí)間: 2025-3-21 18:43
書目名稱Application Specific Processors影響因子(影響力)
書目名稱Application Specific Processors影響因子(影響力)學(xué)科排名
書目名稱Application Specific Processors網(wǎng)絡(luò)公開(kāi)度
書目名稱Application Specific Processors網(wǎng)絡(luò)公開(kāi)度學(xué)科排名
書目名稱Application Specific Processors被引頻次
書目名稱Application Specific Processors被引頻次學(xué)科排名
書目名稱Application Specific Processors年度引用
書目名稱Application Specific Processors年度引用學(xué)科排名
書目名稱Application Specific Processors讀者反饋
書目名稱Application Specific Processors讀者反饋學(xué)科排名
作者: BALE 時(shí)間: 2025-3-21 22:14 作者: 繁殖 時(shí)間: 2025-3-22 03:34 作者: 符合國(guó)情 時(shí)間: 2025-3-22 08:06
Existence of Traces of Null Space Elementso reduce switching activity and improve the performance at the algorithm and circuit level are presented. A new concept to reduce switching activity using combinational self-timed elements and bypassing logic blocks to eliminate redundant operations is proposed.作者: COLIC 時(shí)間: 2025-3-22 12:36
Clifford Algebras and Clifford Modulese of partial vector rotations to approximate the expected one. Under different operating modes, this algorithm can be used either to do Givens transformation for vector rotation and vectoring or to evaluate more than a dozen of elementary, trigonometric, and hyperbolic functions. CORDIC processors a作者: 喃喃訴苦 時(shí)間: 2025-3-22 13:19 作者: 出沒(méi) 時(shí)間: 2025-3-22 19:05
Construction of Elliptic Diffusions,cessor. This advanced system allows us to focus on the parallelization of the Volterra filter algorithm without the expense of VLSI fabrication. When the parallel version of the algorithm is thoroughly tested, our long range goal is to do a VLSI implementation. An application to nonlinear digital sa作者: 情節(jié)劇 時(shí)間: 2025-3-22 23:01 作者: chassis 時(shí)間: 2025-3-23 04:27
Low Power Digital Multipliers,o reduce switching activity and improve the performance at the algorithm and circuit level are presented. A new concept to reduce switching activity using combinational self-timed elements and bypassing logic blocks to eliminate redundant operations is proposed.作者: 陰郁 時(shí)間: 2025-3-23 06:13 作者: 細(xì)微的差異 時(shí)間: 2025-3-23 13:10
Application Specific Processors978-1-4613-1457-8Series ISSN 0893-3405 作者: 火海 時(shí)間: 2025-3-23 15:28
Existence of Traces of Null Space Elementso reduce switching activity and improve the performance at the algorithm and circuit level are presented. A new concept to reduce switching activity using combinational self-timed elements and bypassing logic blocks to eliminate redundant operations is proposed.作者: 擔(dān)心 時(shí)間: 2025-3-23 20:07 作者: conceal 時(shí)間: 2025-3-24 00:47
https://doi.org/10.1007/978-1-4613-1457-8ASIC; CMOS; Computer; algorithms; development; integrated circuit; modeling; processor作者: 擴(kuò)張 時(shí)間: 2025-3-24 04:44 作者: AORTA 時(shí)間: 2025-3-24 07:35
The Springer International Series in Engineering and Computer Sciencehttp://image.papertrans.cn/a/image/159061.jpg作者: exhilaration 時(shí)間: 2025-3-24 13:08 作者: 舊病復(fù)發(fā) 時(shí)間: 2025-3-24 16:32
https://doi.org/10.1007/978-3-319-75895-4s can be implemented with areas and cycle times that are comparable to conventional IEEE double-precision floating point coprocessors. Execution time estimates indicate that the processors are two to three orders of magnitude faster than a conventional software package for variable-precision, interval arithmetic.作者: 無(wú)能力之人 時(shí)間: 2025-3-24 19:32
Variable-Precision, Interval Arithmetic Processors,s can be implemented with areas and cycle times that are comparable to conventional IEEE double-precision floating point coprocessors. Execution time estimates indicate that the processors are two to three orders of magnitude faster than a conventional software package for variable-precision, interval arithmetic.作者: calamity 時(shí)間: 2025-3-24 23:27
0893-3405 itionally, most high performance signal processors have beenrealized with application specific processors. The explanation is thatapplication specific processors can be tailored to exactly match the(usually very demanding) application requirements. The result is thatno `processing power‘ is wasted f作者: 龍蝦 時(shí)間: 2025-3-25 03:30 作者: 濕潤(rùn) 時(shí)間: 2025-3-25 11:02
Modeling the Power Consumption of CMOS Arithmetic Elements,th of the design iterations. Simulation and direct measurement of the performance of test chips is used to evaluate their characteristics, and the results are used to rank the circuits on dynamic power dissipation.作者: 致命 時(shí)間: 2025-3-25 11:56
Variable-Precision, Interval Arithmetic Processors,fy the precision of the computation, determine the accuracy of the results, and recompute inaccurate results with higher precision. The processors support a wide variety of arithmetic operations on variable-precision floating point numbers and intervals. Efficient hardware algorithms and specially d作者: pacific 時(shí)間: 2025-3-25 16:20
Modeling the Power Consumption of CMOS Arithmetic Elements,estimates of the power dissipation of CMOS adders and multipliers, this research aids in the initial circuit choice, thus reducing the number and length of the design iterations. Simulation and direct measurement of the performance of test chips is used to evaluate their characteristics, and the res作者: preeclampsia 時(shí)間: 2025-3-25 23:08 作者: travail 時(shí)間: 2025-3-26 01:57
Low Power Digital Multipliers,o reduce switching activity and improve the performance at the algorithm and circuit level are presented. A new concept to reduce switching activity using combinational self-timed elements and bypassing logic blocks to eliminate redundant operations is proposed.作者: 無(wú)意 時(shí)間: 2025-3-26 05:42
A Unified View of CORDIC Processor Design,e of partial vector rotations to approximate the expected one. Under different operating modes, this algorithm can be used either to do Givens transformation for vector rotation and vectoring or to evaluate more than a dozen of elementary, trigonometric, and hyperbolic functions. CORDIC processors a作者: 衣服 時(shí)間: 2025-3-26 08:56
Multidimensional Systolic Arrays for Computing Discrete Fourier Transforms and Discrete Cosine Transform (DCT) in a multidimensional systolic array. There are extensive applications of fast Fourier transform (FFT) and fast cosine transform (FDCT) algorithms. From the basic principle of fast transform algorithms (breaking the computation in successively smaller computations), we find that the mult作者: 十字架 時(shí)間: 2025-3-26 12:58 作者: 舊病復(fù)發(fā) 時(shí)間: 2025-3-26 18:19 作者: PHON 時(shí)間: 2025-3-26 21:42 作者: gimmick 時(shí)間: 2025-3-27 02:03
Clifford Algebras and Clifford Modulesroach for elementary function evaluation whenever the silicon area is a primary constraint. The main drawback is the intrinsic low performance due to the iterative computational approach. In particular, parallelism cannot be easily introduced since each CORDIC iteration has to select the rotation di作者: interior 時(shí)間: 2025-3-27 07:42
Construction of Elliptic Diffusions,constituent 1-D transforms are required; therefore the entire processing is fully pipelined. This approach is well suited for VLSI implementation by providing simple and regular structures. Complexity estimation of .*.. shows our multidimensional systolic array is within a factor of . of the lower b作者: 星星 時(shí)間: 2025-3-27 11:28
Mathematics and Its Applicationsed with the interconnection of the heterogeneous building blocks into systems with arbitrary topologies. A communication architecture is proposed that allows the interconnection of processors with varying speed and functionalities. Standardization of the Interface Control Unit (ICU) greatly reduces 作者: 蒸發(fā) 時(shí)間: 2025-3-27 14:36
Fault Tolerant Arithmetic,s like sorting networks, FFT arrays, convolvers, and inner product units. This research is significant because the time shared TMR technique proves to be a high reliability, low hardware complexity, and reasonable delay penalty solution to fault tolerant arithmetic.作者: 離開(kāi)真充足 時(shí)間: 2025-3-27 21:06 作者: concert 時(shí)間: 2025-3-28 01:09 作者: 樂(lè)章 時(shí)間: 2025-3-28 04:29
Design and Implementation of an Interface Control Unit for Rapid Prototyping,ed with the interconnection of the heterogeneous building blocks into systems with arbitrary topologies. A communication architecture is proposed that allows the interconnection of processors with varying speed and functionalities. Standardization of the Interface Control Unit (ICU) greatly reduces 作者: hypnogram 時(shí)間: 2025-3-28 09:42 作者: conduct 時(shí)間: 2025-3-28 14:01 作者: 無(wú)王時(shí)期, 時(shí)間: 2025-3-28 16:19
Politische Ideologie im vereinigten Deutschlandgt hat und gegebenenfalls weiterhin beeinflu?t. Bevor nun die Verteilungen und Ver?nderungen der ideologischen Standpunkte der deutschen Bev?lkerung in den 90er Jahren n?her untersucht werden, soll zun?chst der schillernde aber gleichzeitig vorbelastete Begriff der politischen Ideologie etwas n?her 作者: Phonophobia 時(shí)間: 2025-3-28 22:34
Introducing Google Web Toolkit (GWT),ogical and technological fields. The theoretical aspects are based on the performance of precise and reliable experimental data. However, techniques of measurement of various properties of matter near the boundary regions of liquid, solid, or biocolloid systems are relatively few compared to those i作者: 小丑 時(shí)間: 2025-3-29 00:06 作者: 抱怨 時(shí)間: 2025-3-29 04:58
Computational Intelligence in Oncology: Past, Present, and Futureods are applied in different facets of oncology including tumor classification, early prediction and diagnosis, survival prediction, modeling and simulation of cell growth, therapy optimization, and overall cancer management. This chapter aims to present introductory background about the field of On
